llvm/test/CodeGen/ARM/t2-imm.ll

; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s

define i32 @f6(i32 %a) {
; CHECK:f6
; CHECK: movw r0, #:lower16:65537123
; CHECK: movt r0, #:upper16:65537123
    %tmp = add i32 0, 65537123
    ret i32 %tmp
}
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. This should be better than single load from constpool. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82948 91177308-0d34-0410-b5e6-96231b3b80d8 2009-09-27 23:52:58 +00:00			`; RUN: llc < %s -march=arm -mattr=+thumb2 \| FileCheck %s`

			`define i32 @f6(i32 %a) {`
			`; CHECK:f6`
Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83572 91177308-0d34-0410-b5e6-96231b3b80d8 2009-10-08 20:43:22 +00:00			`; CHECK: movw r0, #:lower16:65537123`
			`; CHECK: movt r0, #:upper16:65537123`
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. This should be better than single load from constpool. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82948 91177308-0d34-0410-b5e6-96231b3b80d8 2009-09-27 23:52:58 +00:00			`%tmp = add i32 0, 65537123`
			`ret i32 %tmp`
			`}`