RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-12-14 23:48:49 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
7e4471c842
llvm/test/CodeGen/Mips/nacl-reserved-regs.ll

52 lines
1.7 KiB
LLVM
Raw Normal View History

[mips] Forbid the use of registers t6, t7 and t8 if the target is NaCl. Differential Revision: http://llvm-reviews.chandlerc.com/D2694 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200978 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 17:16:40 +00:00
; RUN: llc -march=mipsel -O3 < %s | FileCheck %s
; RUN: llc -mtriple=mipsel-none-nacl-gnu -O3 < %s \
; RUN: | FileCheck %s -check-prefix=CHECK-NACL
@var = external global i32
define void @f() {
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00
%val1 = load volatile i32, i32* @var
%val2 = load volatile i32, i32* @var
%val3 = load volatile i32, i32* @var
%val4 = load volatile i32, i32* @var
%val5 = load volatile i32, i32* @var
%val6 = load volatile i32, i32* @var
%val7 = load volatile i32, i32* @var
%val8 = load volatile i32, i32* @var
%val9 = load volatile i32, i32* @var
%val10 = load volatile i32, i32* @var
%val11 = load volatile i32, i32* @var
%val12 = load volatile i32, i32* @var
%val13 = load volatile i32, i32* @var
%val14 = load volatile i32, i32* @var
%val15 = load volatile i32, i32* @var
%val16 = load volatile i32, i32* @var
[mips] Forbid the use of registers t6, t7 and t8 if the target is NaCl. Differential Revision: http://llvm-reviews.chandlerc.com/D2694 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200978 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 17:16:40 +00:00
store volatile i32 %val1, i32* @var
store volatile i32 %val2, i32* @var
store volatile i32 %val3, i32* @var
store volatile i32 %val4, i32* @var
store volatile i32 %val5, i32* @var
store volatile i32 %val6, i32* @var
store volatile i32 %val7, i32* @var
store volatile i32 %val8, i32* @var
store volatile i32 %val9, i32* @var
store volatile i32 %val10, i32* @var
store volatile i32 %val11, i32* @var
store volatile i32 %val12, i32* @var
store volatile i32 %val13, i32* @var
store volatile i32 %val14, i32* @var
store volatile i32 %val15, i32* @var
store volatile i32 %val16, i32* @var
ret void
; Check that t6, t7 and t8 are used in non-NaCl code.
; CHECK: lw $14
; CHECK: lw $15
; CHECK: lw $24
; t6, t7 and t8 are reserved in NaCl.
; CHECK-NACL-NOT: lw $14
; CHECK-NACL-NOT: lw $15
; CHECK-NACL-NOT: lw $24
}
Reference in New Issue Copy Permalink