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llvm/lib/Target/PowerPC/PPCScheduleE500mc.td

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Add PPC Freescale e500mc and e5500 subtargets. Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to the PowerPC backend. Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 16:12:39 +00:00
//===-- PPCScheduleE500mc.td - e500mc Scheduling Defs ------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the itinerary class data for the Freescale e500mc 32-bit
// Power processor.
//
// All information is derived from the "e500mc Core Reference Manual",
// Freescale Document Number E500MCRM, Rev. 1, 03/2012.
//
//===----------------------------------------------------------------------===//
// Relevant functional units in the Freescale e500mc core:
//
// * Decode & Dispatch
// Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
// queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
def DIS0 : FuncUnit; // Dispatch stage - insn 1
def DIS1 : FuncUnit; // Dispatch stage - insn 2
// * Execute
// 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
// Some instructions can only execute in SFX0 but not SFX1.
// The CFX has a bypass path, allowing non-divide instructions to execute
// while a divide instruction is executed.
def SFX0 : FuncUnit; // Simple unit 0
def SFX1 : FuncUnit; // Simple unit 1
def BU : FuncUnit; // Branch unit
def CFX_DivBypass
: FuncUnit; // CFX divide bypass path
def CFX_0 : FuncUnit; // CFX pipeline
def LSU_0 : FuncUnit; // LSU pipeline
def FPU_0 : FuncUnit; // FPU pipeline
Greatly simplify the PPC A2 scheduling itinerary As Andy pointed out to me a long time ago, there are no structural hazards in the later pipeline stages of the A2, and so modeling them is useless. Also, modeling the top pre-dispatch stages is deceiving because, when multiple hardware threads are active, those resources are shared among the threads. The bypass definitions were mostly wrong, and so those have been removed. The resulting itinerary is much simpler, and more accurate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190562 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-11 23:25:21 +00:00
def CR_Bypass : Bypass;
Add PPC Freescale e500mc and e5500 subtargets. Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to the PowerPC backend. Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 16:12:39 +00:00
def PPCE500mcItineraries : ProcessorItineraries<
[DIS0, DIS1, SFX0, SFX1, BU, CFX_DivBypass, CFX_0, LSU_0, FPU_0],
[CR_Bypass, GPR_Bypass, FPR_Bypass], [
Add IIC_ prefix to PPC instruction-class names This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195890 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 23:26:09 +00:00
InstrItinData<IIC_IntSimple, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>],
[4, 1, 1], // Latency = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_IntGeneral, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>],
[4, 1, 1], // Latency = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_IntCompare, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>],
[5, 1, 1], // Latency = 1 or 2
[CR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_IntDivW, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [CFX_0], 0>,
InstrStage<14, [CFX_DivBypass]>],
[17, 1, 1], // Latency=4..35, Repeat= 4..35
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_IntMFFS, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<8, [FPU_0]>],
[11], // Latency = 8
[FPR_Bypass]>,
InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<8, [FPU_0]>],
[11, 1, 1], // Latency = 8
[NoBypass, NoBypass, NoBypass]>,
InstrItinData<IIC_IntMulHW, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [CFX_0]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_IntMulHWU, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [CFX_0]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_IntMulLI, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [CFX_0]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_IntRotate, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>],
[4, 1, 1], // Latency = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_IntShift, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>],
[4, 1, 1], // Latency = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_IntTrapW, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<2, [SFX0]>],
[5, 1], // Latency = 2, Repeat rate = 2
[GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_BrB, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [BU]>],
[4, 1], // Latency = 1
[NoBypass, GPR_Bypass]>,
InstrItinData<IIC_BrCR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [BU]>],
[4, 1, 1], // Latency = 1
[CR_Bypass, CR_Bypass, CR_Bypass]>,
InstrItinData<IIC_BrMCR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [BU]>],
[4, 1], // Latency = 1
[CR_Bypass, CR_Bypass]>,
InstrItinData<IIC_BrMCRX, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>],
[4, 1, 1], // Latency = 1
[CR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_LdStDCBA, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3, Repeat rate = 1
[GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_LdStDCBF, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3
[GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_LdStDCBI, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3
[GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_LdStLoad, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3
[GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1], 0>,
InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3
[GPR_Bypass, GPR_Bypass],
2>, // 2 micro-ops
InstrItinData<IIC_LdStStore, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3
[NoBypass, GPR_Bypass]>,
InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1], 0>,
InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3
[NoBypass, GPR_Bypass],
2>, // 2 micro-ops
InstrItinData<IIC_LdStICBI, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3
[NoBypass, GPR_Bypass]>,
InstrItinData<IIC_LdStSTFD, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>],
[6, 1, 1], // Latency = 3
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1], 0>,
InstrStage<1, [LSU_0]>],
[6, 1, 1], // Latency = 3
[GPR_Bypass, GPR_Bypass, GPR_Bypass],
2>, // 2 micro-ops
InstrItinData<IIC_LdStLFD, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>],
[7, 1, 1], // Latency = 4
[FPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_LdStLFDU, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1], 0>,
InstrStage<1, [LSU_0]>],
[7, 1, 1], // Latency = 4
[FPR_Bypass, GPR_Bypass, GPR_Bypass],
2>, // 2 micro-ops
InstrItinData<IIC_LdStLHA, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3
[GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_LdStLHAU, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1], 0>,
InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3
[GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_LdStLMW, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>],
[7, 1], // Latency = r+3
[NoBypass, GPR_Bypass]>,
InstrItinData<IIC_LdStLWARX, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<3, [LSU_0]>],
[6, 1, 1], // Latency = 3, Repeat rate = 3
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3
[NoBypass, GPR_Bypass]>,
InstrItinData<IIC_LdStSync, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>]>,
InstrItinData<IIC_SprMFSR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<4, [SFX0]>],
[7, 1],
[GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_SprMTMSR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<2, [SFX0, SFX1]>],
[5, 1], // Latency = 2, Repeat rate = 4
[GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_SprMTSR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0]>],
[5, 1],
[NoBypass, GPR_Bypass]>,
InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0], 0>]>,
InstrItinData<IIC_SprMFCR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<5, [SFX0]>],
[8, 1],
[GPR_Bypass, CR_Bypass]>,
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<4, [SFX0]>],
[7, 1], // Latency = 4, Repeat rate = 4
[GPR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_SprMFSPR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>],
[4, 1], // Latency = 1, Repeat rate = 1
[GPR_Bypass, CR_Bypass]>,
InstrItinData<IIC_SprMFTB, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<4, [SFX0]>],
[7, 1], // Latency = 4, Repeat rate = 4
[NoBypass, GPR_Bypass]>,
InstrItinData<IIC_SprMTSPR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>],
[4, 1], // Latency = 1, Repeat rate = 1
[CR_Bypass, GPR_Bypass]>,
InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0]>],
[4, 1],
[NoBypass, GPR_Bypass]>,
InstrItinData<IIC_FPGeneral, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<2, [FPU_0]>],
[11, 1, 1], // Latency = 8, Repeat rate = 2
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<IIC_FPAddSub, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<4, [FPU_0]>],
[13, 1, 1], // Latency = 10, Repeat rate = 4
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<IIC_FPCompare, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<2, [FPU_0]>],
[11, 1, 1], // Latency = 8, Repeat rate = 2
[CR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<IIC_FPDivD, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<68, [FPU_0]>],
[71, 1, 1], // Latency = 68, Repeat rate = 68
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<IIC_FPDivS, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<38, [FPU_0]>],
[41, 1, 1], // Latency = 38, Repeat rate = 38
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<IIC_FPFused, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<4, [FPU_0]>],
[13, 1, 1, 1], // Latency = 10, Repeat rate = 4
[FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<IIC_FPRes, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<38, [FPU_0]>],
[41, 1], // Latency = 38, Repeat rate = 38
[FPR_Bypass, FPR_Bypass]>
Add PPC Freescale e500mc and e5500 subtargets. Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to the PowerPC backend. Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 16:12:39 +00:00
]>;
// ===---------------------------------------------------------------------===//
// e500mc machine model for scheduling and other instruction cost heuristics.
def PPCE500mcModel : SchedMachineModel {
let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
let LoadLatency = 5; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
let Itineraries = PPCE500mcItineraries;
}
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