2012-02-18 12:03:15 +00:00
|
|
|
//===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===//
|
|
|
|
//
|
2004-02-25 20:52:20 +00:00
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
2007-12-29 20:36:04 +00:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2012-02-18 12:03:15 +00:00
|
|
|
//
|
2004-02-25 20:52:20 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2004-09-22 21:38:42 +00:00
|
|
|
|
2013-06-04 18:33:25 +00:00
|
|
|
class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: Instruction {
|
2005-12-18 08:21:00 +00:00
|
|
|
field bits<32> Inst;
|
|
|
|
|
2006-02-05 05:50:24 +00:00
|
|
|
let Namespace = "SP";
|
2014-01-06 08:08:58 +00:00
|
|
|
let Size = 4;
|
2005-12-18 08:21:00 +00:00
|
|
|
|
|
|
|
bits<2> op;
|
|
|
|
let Inst{31-30} = op; // Top two bits are the 'op' field
|
2013-06-04 18:33:25 +00:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
dag OutOperandList = outs;
|
|
|
|
dag InOperandList = ins;
|
2005-12-18 08:21:00 +00:00
|
|
|
let AsmString = asmstr;
|
|
|
|
let Pattern = pattern;
|
2014-01-06 08:08:58 +00:00
|
|
|
|
|
|
|
let DecoderNamespace = "Sparc";
|
|
|
|
field bits<32> SoftFail = 0;
|
2005-12-18 08:21:00 +00:00
|
|
|
}
|
|
|
|
|
2004-09-22 21:38:42 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2006-02-05 05:50:24 +00:00
|
|
|
// Format #2 instruction classes in the Sparc
|
2004-09-22 21:38:42 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2005-12-18 08:21:00 +00:00
|
|
|
// Format 2 instructions
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSP<outs, ins, asmstr, pattern> {
|
2004-09-22 21:38:42 +00:00
|
|
|
bits<3> op2;
|
|
|
|
bits<22> imm22;
|
|
|
|
let op = 0; // op = 0
|
|
|
|
let Inst{24-22} = op2;
|
|
|
|
let Inst{21-0} = imm22;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Specific F2 classes: SparcV8 manual, page 44
|
2004-02-25 20:52:20 +00:00
|
|
|
//
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: F2<outs, ins, asmstr, pattern> {
|
2004-09-22 21:38:42 +00:00
|
|
|
bits<5> rd;
|
|
|
|
|
|
|
|
let op2 = op2Val;
|
|
|
|
|
|
|
|
let Inst{29-25} = rd;
|
|
|
|
}
|
|
|
|
|
2014-03-01 20:08:48 +00:00
|
|
|
class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
|
2004-09-22 21:38:42 +00:00
|
|
|
bits<4> cond;
|
|
|
|
let op2 = op2Val;
|
|
|
|
|
|
|
|
let Inst{29} = annul;
|
|
|
|
let Inst{28-25} = cond;
|
|
|
|
}
|
|
|
|
|
2014-03-01 22:03:07 +00:00
|
|
|
class F2_3<bits<3> op2Val, bit annul, bit pred,
|
|
|
|
dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSP<outs, ins, asmstr, pattern> {
|
|
|
|
bits<2> cc;
|
2014-01-06 08:08:58 +00:00
|
|
|
bits<4> cond;
|
|
|
|
bits<19> imm19;
|
|
|
|
|
|
|
|
let op = 0; // op = 0
|
|
|
|
|
|
|
|
let Inst{29} = annul;
|
|
|
|
let Inst{28-25} = cond;
|
|
|
|
let Inst{24-22} = op2Val;
|
2014-03-01 22:03:07 +00:00
|
|
|
let Inst{21-20} = cc;
|
2014-01-06 08:08:58 +00:00
|
|
|
let Inst{19} = pred;
|
|
|
|
let Inst{18-0} = imm19;
|
|
|
|
}
|
|
|
|
|
2004-09-22 21:38:42 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2006-02-05 05:50:24 +00:00
|
|
|
// Format #3 instruction classes in the Sparc
|
2004-02-25 20:52:20 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSP<outs, ins, asmstr, pattern> {
|
2004-02-25 20:52:20 +00:00
|
|
|
bits<5> rd;
|
|
|
|
bits<6> op3;
|
|
|
|
bits<5> rs1;
|
|
|
|
let op{1} = 1; // Op = 2 or 3
|
|
|
|
let Inst{29-25} = rd;
|
|
|
|
let Inst{24-19} = op3;
|
|
|
|
let Inst{18-14} = rs1;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Specific F3 classes: SparcV8 manual, page 44
|
|
|
|
//
|
2014-02-07 07:34:49 +00:00
|
|
|
class F3_1_asi<bits<2> opVal, bits<6> op3val, bits<8> asi, dag outs, dag ins,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
|
2004-02-25 20:52:20 +00:00
|
|
|
bits<5> rs2;
|
|
|
|
|
|
|
|
let op = opVal;
|
|
|
|
let op3 = op3val;
|
|
|
|
|
|
|
|
let Inst{13} = 0; // i field = 0
|
|
|
|
let Inst{12-5} = asi; // address space identifier
|
|
|
|
let Inst{4-0} = rs2;
|
|
|
|
}
|
|
|
|
|
2014-02-07 07:34:49 +00:00
|
|
|
class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr,
|
|
|
|
list<dag> pattern> : F3_1_asi<opVal, op3val, 0, outs, ins,
|
|
|
|
asmstr, pattern>;
|
|
|
|
|
2013-06-04 18:33:25 +00:00
|
|
|
class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
|
2004-02-25 20:52:20 +00:00
|
|
|
bits<13> simm13;
|
|
|
|
|
|
|
|
let op = opVal;
|
|
|
|
let op3 = op3val;
|
|
|
|
|
|
|
|
let Inst{13} = 1; // i field = 1
|
|
|
|
let Inst{12-0} = simm13;
|
|
|
|
}
|
|
|
|
|
2004-06-18 06:28:21 +00:00
|
|
|
// floating-point
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
|
|
|
|
string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
|
2004-02-25 20:52:20 +00:00
|
|
|
bits<5> rs2;
|
|
|
|
|
|
|
|
let op = opVal;
|
|
|
|
let op3 = op3val;
|
|
|
|
|
2004-06-18 06:28:21 +00:00
|
|
|
let Inst{13-5} = opfval; // fp opcode
|
2004-02-25 20:52:20 +00:00
|
|
|
let Inst{4-0} = rs2;
|
|
|
|
}
|
2006-09-01 22:28:02 +00:00
|
|
|
|
2013-09-22 09:54:42 +00:00
|
|
|
// floating-point unary operations.
|
|
|
|
class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
|
|
|
|
string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
|
|
|
|
bits<5> rs2;
|
|
|
|
|
|
|
|
let op = opVal;
|
|
|
|
let op3 = op3val;
|
|
|
|
let rs1 = 0;
|
|
|
|
|
|
|
|
let Inst{13-5} = opfval; // fp opcode
|
|
|
|
let Inst{4-0} = rs2;
|
|
|
|
}
|
|
|
|
|
|
|
|
// floating-point compares.
|
|
|
|
class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
|
|
|
|
string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
|
|
|
|
bits<5> rs2;
|
|
|
|
|
|
|
|
let op = opVal;
|
|
|
|
let op3 = op3val;
|
|
|
|
|
|
|
|
let Inst{13-5} = opfval; // fp opcode
|
|
|
|
let Inst{4-0} = rs2;
|
|
|
|
}
|
|
|
|
|
2013-04-02 04:09:12 +00:00
|
|
|
// Shift by register rs2.
|
|
|
|
class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
|
|
|
|
string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
|
|
|
|
bit x = xVal; // 1 for 64-bit shifts.
|
|
|
|
bits<5> rs2;
|
|
|
|
|
|
|
|
let op = opVal;
|
|
|
|
let op3 = op3val;
|
|
|
|
|
|
|
|
let Inst{13} = 0; // i field = 0
|
|
|
|
let Inst{12} = x; // extended registers.
|
|
|
|
let Inst{4-0} = rs2;
|
|
|
|
}
|
2006-09-01 22:28:02 +00:00
|
|
|
|
2013-04-02 04:09:12 +00:00
|
|
|
// Shift by immediate.
|
|
|
|
class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
|
|
|
|
string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
|
|
|
|
bit x = xVal; // 1 for 64-bit shifts.
|
|
|
|
bits<6> shcnt; // shcnt32 / shcnt64.
|
|
|
|
|
|
|
|
let op = opVal;
|
|
|
|
let op3 = op3val;
|
|
|
|
|
|
|
|
let Inst{13} = 1; // i field = 1
|
|
|
|
let Inst{12} = x; // extended registers.
|
|
|
|
let Inst{5-0} = shcnt;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Define rr and ri shift instructions with patterns.
|
|
|
|
multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
|
|
|
|
ValueType VT, RegisterClass RC> {
|
2014-01-08 07:47:57 +00:00
|
|
|
def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
|
|
|
|
!strconcat(OpcStr, " $rs1, $rs2, $rd"),
|
|
|
|
[(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>;
|
|
|
|
def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt),
|
|
|
|
!strconcat(OpcStr, " $rs1, $shcnt, $rd"),
|
|
|
|
[(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>;
|
2013-04-02 04:09:12 +00:00
|
|
|
}
|
2013-09-22 09:18:26 +00:00
|
|
|
|
|
|
|
class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSP<outs, ins, asmstr, pattern> {
|
|
|
|
bits<5> rd;
|
|
|
|
|
|
|
|
let op = 2;
|
|
|
|
let Inst{29-25} = rd;
|
|
|
|
let Inst{24-19} = op3;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
class F4_1<bits<6> op3, dag outs, dag ins,
|
|
|
|
string asmstr, list<dag> pattern>
|
|
|
|
: F4<op3, outs, ins, asmstr, pattern> {
|
|
|
|
|
2014-03-02 04:43:45 +00:00
|
|
|
bit intcc;
|
|
|
|
bits<2> cc;
|
2013-09-22 09:18:26 +00:00
|
|
|
bits<4> cond;
|
|
|
|
bits<5> rs2;
|
|
|
|
|
|
|
|
let Inst{4-0} = rs2;
|
2014-03-02 04:43:45 +00:00
|
|
|
let Inst{12-11} = cc;
|
2013-09-22 09:18:26 +00:00
|
|
|
let Inst{13} = 0;
|
|
|
|
let Inst{17-14} = cond;
|
2014-03-02 04:43:45 +00:00
|
|
|
let Inst{18} = intcc;
|
2013-09-22 09:18:26 +00:00
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
class F4_2<bits<6> op3, dag outs, dag ins,
|
|
|
|
string asmstr, list<dag> pattern>
|
|
|
|
: F4<op3, outs, ins, asmstr, pattern> {
|
2014-03-02 04:43:45 +00:00
|
|
|
bit intcc;
|
|
|
|
bits<2> cc;
|
2013-09-22 09:18:26 +00:00
|
|
|
bits<4> cond;
|
|
|
|
bits<11> simm11;
|
|
|
|
|
|
|
|
let Inst{10-0} = simm11;
|
2014-03-02 04:43:45 +00:00
|
|
|
let Inst{12-11} = cc;
|
2013-09-22 09:18:26 +00:00
|
|
|
let Inst{13} = 1;
|
|
|
|
let Inst{17-14} = cond;
|
2014-03-02 04:43:45 +00:00
|
|
|
let Inst{18} = intcc;
|
2013-09-22 09:18:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,
|
|
|
|
string asmstr, list<dag> pattern>
|
|
|
|
: F4<op3, outs, ins, asmstr, pattern> {
|
|
|
|
bits<4> cond;
|
2014-03-02 04:43:45 +00:00
|
|
|
bit intcc;
|
|
|
|
bits<2> opf_cc;
|
2013-09-22 09:18:26 +00:00
|
|
|
bits<5> rs2;
|
|
|
|
|
|
|
|
let Inst{18} = 0;
|
|
|
|
let Inst{17-14} = cond;
|
2014-03-02 04:43:45 +00:00
|
|
|
let Inst{13} = intcc;
|
|
|
|
let Inst{12-11} = opf_cc;
|
2013-09-22 09:18:26 +00:00
|
|
|
let Inst{10-5} = opf_low;
|
|
|
|
let Inst{4-0} = rs2;
|
|
|
|
}
|