llvm/test/CodeGen/Mips/frame-address.ll

; RUN: llc -march=mipsel < %s | FileCheck %s

declare i8* @llvm.frameaddress(i32) nounwind readnone

define i8* @f() nounwind {
entry:
  %0 = call i8* @llvm.frameaddress(i32 0)
  ret i8* %0

; CHECK:   move    $fp, $sp
; CHECK:   move    $2, $fp
}
Drop support for Mips1 and Mips2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8 2011-09-09 20:45:50 +00:00			`; RUN: llc -march=mipsel < %s \| FileCheck %s`
Test case for r132444. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132445 91177308-0d34-0410-b5e6-96231b3b80d8 2011-06-02 00:25:53 +00:00
			`declare i8* @llvm.frameaddress(i32) nounwind readnone`

			`define i8* @f() nounwind {`
			`entry:`
			`%0 = call i8* @llvm.frameaddress(i32 0)`
			`ret i8* %0`

This patch that sets the EmitAlias flag in td files and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8 2013-02-05 08:32:10 +00:00			`; CHECK: move $fp, $sp`
[mips] Print move instructions. "move $4, $5" is printed instead of "or $4, $5, $zero". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176455 91177308-0d34-0410-b5e6-96231b3b80d8 2013-03-04 22:25:01 +00:00			`; CHECK: move $2, $fp`
Test case for r132444. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132445 91177308-0d34-0410-b5e6-96231b3b80d8 2011-06-02 00:25:53 +00:00			`}`