2010-04-21 18:02:42 +00:00
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//===-- RegAllocFast.cpp - A fast register allocator for debug code -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This register allocator allocates registers to a basic block at a time,
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// attempting to keep values in registers and reusing registers as appropriate.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "llvm/BasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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#include <algorithm>
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using namespace llvm;
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2010-05-14 20:28:32 +00:00
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static cl::opt<bool> VerifyFastRegalloc("verify-fast-regalloc", cl::Hidden,
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cl::desc("Verify machine code before fast regalloc"));
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2010-04-21 18:02:42 +00:00
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STATISTIC(NumStores, "Number of stores added");
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STATISTIC(NumLoads , "Number of loads added");
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2010-05-14 21:55:50 +00:00
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STATISTIC(NumCopies, "Number of copies coalesced");
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2010-04-21 18:02:42 +00:00
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static RegisterRegAlloc
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fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
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namespace {
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class RAFast : public MachineFunctionPass {
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public:
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static char ID;
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2010-05-14 00:02:20 +00:00
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RAFast() : MachineFunctionPass(&ID), StackSlotForVirtReg(-1),
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2010-05-17 02:07:32 +00:00
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isBulkSpilling(false) {}
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2010-04-21 18:02:42 +00:00
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private:
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const TargetMachine *TM;
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MachineFunction *MF;
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2010-05-13 00:19:43 +00:00
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MachineRegisterInfo *MRI;
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2010-04-21 18:02:42 +00:00
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const TargetRegisterInfo *TRI;
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const TargetInstrInfo *TII;
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2010-05-17 02:07:22 +00:00
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// Basic block currently being allocated.
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MachineBasicBlock *MBB;
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2010-04-21 18:02:42 +00:00
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// StackSlotForVirtReg - Maps virtual regs to the frame index where these
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// values are spilled.
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IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
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2010-05-11 23:24:45 +00:00
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// Everything we know about a live virtual register.
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struct LiveReg {
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2010-05-11 23:24:47 +00:00
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MachineInstr *LastUse; // Last instr to use reg.
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unsigned PhysReg; // Currently held here.
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unsigned short LastOpNum; // OpNum on LastUse.
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bool Dirty; // Register needs spill.
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2010-05-11 23:24:45 +00:00
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2010-05-11 23:24:47 +00:00
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LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0),
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2010-05-17 02:07:29 +00:00
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Dirty(false) {}
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2010-05-11 23:24:45 +00:00
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};
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typedef DenseMap<unsigned, LiveReg> LiveRegMap;
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2010-05-17 02:07:29 +00:00
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typedef LiveRegMap::value_type LiveRegEntry;
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2010-05-11 23:24:45 +00:00
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// LiveVirtRegs - This map contains entries for each virtual register
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2010-04-21 18:02:42 +00:00
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// that is currently available in a physical register.
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2010-05-11 23:24:45 +00:00
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LiveRegMap LiveVirtRegs;
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2010-04-21 18:02:42 +00:00
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2010-05-11 18:54:45 +00:00
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// RegState - Track the state of a physical register.
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enum RegState {
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// A disabled register is not available for allocation, but an alias may
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// be in use. A register can only be moved out of the disabled state if
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// all aliases are disabled.
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regDisabled,
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// A free register is not currently in use and can be allocated
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// immediately without checking aliases.
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regFree,
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// A reserved register has been assigned expolicitly (e.g., setting up a
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// call parameter), and it remains reserved until it is used.
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regReserved
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2010-04-21 18:02:42 +00:00
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2010-05-11 18:54:45 +00:00
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// A register state may also be a virtual register number, indication that
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// the physical register is currently allocated to a virtual register. In
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2010-05-11 23:24:45 +00:00
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// that case, LiveVirtRegs contains the inverse mapping.
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2010-05-11 18:54:45 +00:00
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};
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// PhysRegState - One of the RegState enums, or a virtreg.
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std::vector<unsigned> PhysRegState;
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2010-04-21 18:02:42 +00:00
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// UsedInInstr - BitVector of physregs that are used in the current
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// instruction, and so cannot be allocated.
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BitVector UsedInInstr;
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2010-05-14 22:02:56 +00:00
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// Allocatable - vector of allocatable physical registers.
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BitVector Allocatable;
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2010-04-21 18:02:42 +00:00
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2010-05-17 02:07:32 +00:00
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// isBulkSpilling - This flag is set when LiveRegMap will be cleared
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// completely after spilling all live registers. LiveRegMap entries should
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// not be erased.
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bool isBulkSpilling;
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2010-05-14 00:02:20 +00:00
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2010-04-21 18:02:42 +00:00
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public:
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virtual const char *getPassName() const {
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return "Fast Register Allocator";
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequiredID(PHIEliminationID);
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AU.addRequiredID(TwoAddressInstructionPassID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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bool runOnMachineFunction(MachineFunction &Fn);
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2010-05-17 02:07:22 +00:00
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void AllocateBasicBlock();
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2010-04-21 18:02:42 +00:00
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int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
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2010-05-15 06:09:08 +00:00
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bool isLastUseOfLocalReg(MachineOperand&);
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2010-05-17 02:07:29 +00:00
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void addKillFlag(const LiveReg&);
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2010-05-17 02:49:15 +00:00
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void killVirtReg(LiveRegMap::iterator);
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2010-05-12 18:46:03 +00:00
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void killVirtReg(unsigned VirtReg);
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2010-05-17 02:49:15 +00:00
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void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator);
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2010-05-17 02:07:32 +00:00
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void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
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2010-05-14 18:03:25 +00:00
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void usePhysReg(MachineOperand&);
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2010-05-17 02:07:22 +00:00
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void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
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2010-05-17 02:07:29 +00:00
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void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg);
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void allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint);
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2010-05-17 03:26:09 +00:00
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LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum,
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unsigned VirtReg, unsigned Hint);
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LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum,
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unsigned VirtReg, unsigned Hint);
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2010-05-17 02:07:22 +00:00
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void spillAll(MachineInstr *MI);
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2010-05-17 02:49:21 +00:00
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bool setPhysReg(MachineOperand &MO, unsigned PhysReg);
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2010-04-21 18:02:42 +00:00
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};
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char RAFast::ID = 0;
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}
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/// getStackSpaceFor - This allocates space for the specified virtual register
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/// to be held on the stack.
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int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
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// Find the location Reg would belong...
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int SS = StackSlotForVirtReg[VirtReg];
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if (SS != -1)
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return SS; // Already has space allocated?
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// Allocate a new stack object for this spill location...
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int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
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RC->getAlignment());
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// Assign the slot.
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StackSlotForVirtReg[VirtReg] = FrameIdx;
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return FrameIdx;
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}
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2010-05-15 06:09:08 +00:00
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/// isLastUseOfLocalReg - Return true if MO is the only remaining reference to
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/// its virtual register, and it is guaranteed to be a block-local register.
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///
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bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) {
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// Check for non-debug uses or defs following MO.
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// This is the most likely way to fail - fast path it.
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2010-05-17 02:49:15 +00:00
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MachineOperand *Next = &MO;
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while ((Next = Next->getNextOperandForReg()))
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if (!Next->isDebug())
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2010-05-15 06:09:08 +00:00
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return false;
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// If the register has ever been spilled or reloaded, we conservatively assume
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// it is a global register used in multiple blocks.
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if (StackSlotForVirtReg[MO.getReg()] != -1)
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return false;
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// Check that the use/def chain has exactly one operand - MO.
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return &MRI->reg_nodbg_begin(MO.getReg()).getOperand() == &MO;
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}
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2010-05-12 18:46:03 +00:00
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/// addKillFlag - Set kill flags on last use of a virtual register.
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2010-05-17 02:07:29 +00:00
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void RAFast::addKillFlag(const LiveReg &LR) {
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if (!LR.LastUse) return;
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MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
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if (MO.isDef())
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MO.setIsDead();
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else if (!LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum))
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MO.setIsKill();
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2010-05-12 18:46:03 +00:00
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}
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/// killVirtReg - Mark virtreg as no longer available.
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2010-05-17 02:49:15 +00:00
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void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
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addKillFlag(LRI->second);
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const LiveReg &LR = LRI->second;
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assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
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2010-05-12 18:46:03 +00:00
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PhysRegState[LR.PhysReg] = regFree;
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2010-05-17 02:07:32 +00:00
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// Erase from LiveVirtRegs unless we're spilling in bulk.
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if (!isBulkSpilling)
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2010-05-17 02:49:15 +00:00
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LiveVirtRegs.erase(LRI);
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2010-05-11 23:24:45 +00:00
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}
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2010-05-11 18:54:45 +00:00
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/// killVirtReg - Mark virtreg as no longer available.
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void RAFast::killVirtReg(unsigned VirtReg) {
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"killVirtReg needs a virtual register");
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2010-05-17 02:49:15 +00:00
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LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg);
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if (LRI != LiveVirtRegs.end())
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killVirtReg(LRI);
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2010-04-21 18:02:42 +00:00
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}
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2010-05-11 18:54:45 +00:00
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/// spillVirtReg - This method spills the value specified by VirtReg into the
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/// corresponding stack slot if needed. If isKill is set, the register is also
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/// killed.
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2010-05-17 02:07:32 +00:00
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void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {
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2010-05-11 18:54:45 +00:00
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"Spilling a physical register is illegal!");
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2010-05-17 02:49:15 +00:00
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LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg);
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assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register");
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spillVirtReg(MI, LRI);
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2010-05-14 00:02:20 +00:00
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}
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/// spillVirtReg - Do the actual work of spilling.
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2010-05-17 02:07:22 +00:00
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void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
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2010-05-17 02:49:15 +00:00
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LiveRegMap::iterator LRI) {
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LiveReg &LR = LRI->second;
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assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
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2010-05-11 23:24:45 +00:00
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2010-05-11 23:24:47 +00:00
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if (LR.Dirty) {
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2010-05-17 02:07:32 +00:00
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// If this physreg is used by the instruction, we want to kill it on the
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// instruction, not on the spill.
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2010-05-17 02:49:15 +00:00
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bool SpillKill = LR.LastUse != MI;
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2010-05-11 23:24:47 +00:00
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LR.Dirty = false;
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2010-05-17 02:49:15 +00:00
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DEBUG(dbgs() << "Spilling %reg" << LRI->first
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2010-05-14 00:02:20 +00:00
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<< " in " << TRI->getName(LR.PhysReg));
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2010-05-17 02:49:15 +00:00
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const TargetRegisterClass *RC = MRI->getRegClass(LRI->first);
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int FI = getStackSpaceFor(LRI->first, RC);
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2010-05-17 02:07:22 +00:00
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DEBUG(dbgs() << " to stack slot #" << FI << "\n");
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2010-05-17 02:49:15 +00:00
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TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
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2010-04-21 18:02:42 +00:00
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++NumStores; // Update statistics
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2010-05-17 02:49:15 +00:00
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if (SpillKill)
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2010-05-11 23:24:47 +00:00
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LR.LastUse = 0; // Don't kill register again
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2010-05-11 18:54:45 +00:00
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}
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2010-05-17 02:49:15 +00:00
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killVirtReg(LRI);
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2010-04-21 18:02:42 +00:00
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}
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2010-05-11 18:54:45 +00:00
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/// spillAll - Spill all dirty virtregs without killing them.
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2010-05-17 02:07:22 +00:00
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void RAFast::spillAll(MachineInstr *MI) {
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2010-05-17 02:07:32 +00:00
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isBulkSpilling = true;
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2010-05-11 23:24:45 +00:00
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for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
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e = LiveVirtRegs.end(); i != e; ++i)
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2010-05-17 02:07:32 +00:00
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spillVirtReg(MI, i);
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LiveVirtRegs.clear();
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isBulkSpilling = false;
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2010-05-11 18:54:45 +00:00
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}
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2010-04-21 18:02:42 +00:00
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2010-05-14 18:03:25 +00:00
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/// usePhysReg - Handle the direct use of a physical register.
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/// Check that the register is not used by a virtreg.
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/// Kill the physreg, marking it free.
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/// This may add implicit kills to MO->getParent() and invalidate MO.
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void RAFast::usePhysReg(MachineOperand &MO) {
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unsigned PhysReg = MO.getReg();
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assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
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"Bad usePhysReg operand");
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switch (PhysRegState[PhysReg]) {
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2010-05-11 18:54:45 +00:00
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case regDisabled:
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break;
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case regReserved:
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PhysRegState[PhysReg] = regFree;
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2010-05-14 18:03:25 +00:00
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// Fall through
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case regFree:
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UsedInInstr.set(PhysReg);
|
|
|
|
MO.setIsKill();
|
2010-05-11 18:54:45 +00:00
|
|
|
return;
|
|
|
|
default:
|
2010-05-14 18:03:25 +00:00
|
|
|
// The physreg was allocated to a virtual register. That means to value we
|
|
|
|
// wanted has been clobbered.
|
|
|
|
llvm_unreachable("Instruction uses an allocated register");
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-14 18:03:25 +00:00
|
|
|
// Maybe a superregister is reserved?
|
2010-05-11 18:54:45 +00:00
|
|
|
for (const unsigned *AS = TRI->getAliasSet(PhysReg);
|
|
|
|
unsigned Alias = *AS; ++AS) {
|
2010-05-14 18:03:25 +00:00
|
|
|
switch (PhysRegState[Alias]) {
|
2010-05-11 18:54:45 +00:00
|
|
|
case regDisabled:
|
|
|
|
break;
|
|
|
|
case regReserved:
|
2010-05-14 18:03:25 +00:00
|
|
|
assert(TRI->isSuperRegister(PhysReg, Alias) &&
|
|
|
|
"Instruction is not using a subregister of a reserved register");
|
|
|
|
// Leave the superregister in the working set.
|
2010-05-11 18:54:45 +00:00
|
|
|
PhysRegState[Alias] = regFree;
|
2010-05-14 18:03:25 +00:00
|
|
|
UsedInInstr.set(Alias);
|
|
|
|
MO.getParent()->addRegisterKilled(Alias, TRI, true);
|
|
|
|
return;
|
|
|
|
case regFree:
|
|
|
|
if (TRI->isSuperRegister(PhysReg, Alias)) {
|
|
|
|
// Leave the superregister in the working set.
|
|
|
|
UsedInInstr.set(Alias);
|
|
|
|
MO.getParent()->addRegisterKilled(Alias, TRI, true);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
// Some other alias was in the working set - clear it.
|
|
|
|
PhysRegState[Alias] = regDisabled;
|
2010-05-11 18:54:45 +00:00
|
|
|
break;
|
|
|
|
default:
|
2010-05-14 18:03:25 +00:00
|
|
|
llvm_unreachable("Instruction uses an alias of an allocated register");
|
2010-05-11 18:54:45 +00:00
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
2010-05-14 18:03:25 +00:00
|
|
|
|
|
|
|
// All aliases are disabled, bring register into working set.
|
|
|
|
PhysRegState[PhysReg] = regFree;
|
|
|
|
UsedInInstr.set(PhysReg);
|
|
|
|
MO.setIsKill();
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-14 18:03:25 +00:00
|
|
|
/// definePhysReg - Mark PhysReg as reserved or free after spilling any
|
|
|
|
/// virtregs. This is very similar to defineVirtReg except the physreg is
|
|
|
|
/// reserved instead of allocated.
|
2010-05-17 02:07:22 +00:00
|
|
|
void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg,
|
|
|
|
RegState NewState) {
|
2010-05-14 18:03:25 +00:00
|
|
|
UsedInInstr.set(PhysReg);
|
2010-05-11 18:54:45 +00:00
|
|
|
switch (unsigned VirtReg = PhysRegState[PhysReg]) {
|
|
|
|
case regDisabled:
|
|
|
|
break;
|
2010-05-14 18:03:25 +00:00
|
|
|
default:
|
2010-05-17 02:07:32 +00:00
|
|
|
spillVirtReg(MI, VirtReg);
|
2010-05-14 18:03:25 +00:00
|
|
|
// Fall through.
|
2010-05-11 18:54:45 +00:00
|
|
|
case regFree:
|
|
|
|
case regReserved:
|
2010-05-14 18:03:25 +00:00
|
|
|
PhysRegState[PhysReg] = NewState;
|
2010-05-11 18:54:45 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-05-14 18:03:25 +00:00
|
|
|
// This is a disabled register, disable all aliases.
|
|
|
|
PhysRegState[PhysReg] = NewState;
|
2010-05-11 18:54:45 +00:00
|
|
|
for (const unsigned *AS = TRI->getAliasSet(PhysReg);
|
|
|
|
unsigned Alias = *AS; ++AS) {
|
2010-05-14 18:03:25 +00:00
|
|
|
UsedInInstr.set(Alias);
|
2010-05-11 18:54:45 +00:00
|
|
|
switch (unsigned VirtReg = PhysRegState[Alias]) {
|
|
|
|
case regDisabled:
|
|
|
|
break;
|
|
|
|
default:
|
2010-05-17 02:07:32 +00:00
|
|
|
spillVirtReg(MI, VirtReg);
|
2010-05-14 18:03:25 +00:00
|
|
|
// Fall through.
|
|
|
|
case regFree:
|
|
|
|
case regReserved:
|
|
|
|
PhysRegState[Alias] = regDisabled;
|
|
|
|
if (TRI->isSuperRegister(PhysReg, Alias))
|
|
|
|
return;
|
2010-05-11 18:54:45 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-14 18:03:25 +00:00
|
|
|
|
2010-04-21 18:02:42 +00:00
|
|
|
/// assignVirtToPhysReg - This method updates local state so that we know
|
|
|
|
/// that PhysReg is the proper container for VirtReg now. The physical
|
|
|
|
/// register must not be used for anything else when this is called.
|
|
|
|
///
|
2010-05-17 02:07:29 +00:00
|
|
|
void RAFast::assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg) {
|
|
|
|
DEBUG(dbgs() << "Assigning %reg" << LRE.first << " to "
|
2010-05-11 18:54:45 +00:00
|
|
|
<< TRI->getName(PhysReg) << "\n");
|
2010-05-17 02:07:29 +00:00
|
|
|
PhysRegState[PhysReg] = LRE.first;
|
|
|
|
assert(!LRE.second.PhysReg && "Already assigned a physreg");
|
|
|
|
LRE.second.PhysReg = PhysReg;
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
/// allocVirtReg - Allocate a physical register for VirtReg.
|
2010-05-17 02:07:29 +00:00
|
|
|
void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
|
2010-05-17 02:49:15 +00:00
|
|
|
const unsigned SpillCost = 100;
|
2010-05-17 02:07:29 +00:00
|
|
|
const unsigned VirtReg = LRE.first;
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
|
|
|
|
"Can only allocate virtual registers");
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-13 00:19:43 +00:00
|
|
|
const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
|
2010-05-11 18:54:45 +00:00
|
|
|
TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF);
|
|
|
|
TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF);
|
|
|
|
|
2010-05-13 00:19:43 +00:00
|
|
|
// Ignore invalid hints.
|
|
|
|
if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
|
2010-05-15 10:23:23 +00:00
|
|
|
!RC->contains(Hint) || UsedInInstr.test(Hint) ||
|
|
|
|
!Allocatable.test(Hint)))
|
2010-05-13 00:19:43 +00:00
|
|
|
Hint = 0;
|
|
|
|
|
|
|
|
// Take hint when possible.
|
|
|
|
if (Hint) {
|
|
|
|
assert(RC->contains(Hint) && !UsedInInstr.test(Hint) &&
|
2010-05-14 22:02:56 +00:00
|
|
|
Allocatable.test(Hint) && "Invalid hint should have been cleared");
|
2010-05-13 00:19:43 +00:00
|
|
|
switch(PhysRegState[Hint]) {
|
|
|
|
case regDisabled:
|
|
|
|
case regReserved:
|
|
|
|
break;
|
|
|
|
default:
|
2010-05-17 02:07:32 +00:00
|
|
|
spillVirtReg(MI, PhysRegState[Hint]);
|
2010-05-13 00:19:43 +00:00
|
|
|
// Fall through.
|
|
|
|
case regFree:
|
2010-05-17 02:07:29 +00:00
|
|
|
return assignVirtToPhysReg(LRE, Hint);
|
2010-05-13 00:19:43 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// First try to find a completely free register.
|
|
|
|
unsigned BestCost = 0, BestReg = 0;
|
|
|
|
bool hasDisabled = false;
|
|
|
|
for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
|
|
|
|
unsigned PhysReg = *I;
|
|
|
|
switch(PhysRegState[PhysReg]) {
|
|
|
|
case regDisabled:
|
|
|
|
hasDisabled = true;
|
|
|
|
case regReserved:
|
|
|
|
continue;
|
|
|
|
case regFree:
|
2010-05-11 23:24:45 +00:00
|
|
|
if (!UsedInInstr.test(PhysReg))
|
2010-05-17 02:07:29 +00:00
|
|
|
return assignVirtToPhysReg(LRE, PhysReg);
|
2010-05-11 18:54:45 +00:00
|
|
|
continue;
|
|
|
|
default:
|
|
|
|
// Grab the first spillable register we meet.
|
2010-05-11 23:24:47 +00:00
|
|
|
if (!BestReg && !UsedInInstr.test(PhysReg))
|
2010-05-17 02:49:15 +00:00
|
|
|
BestReg = PhysReg, BestCost = SpillCost;
|
2010-05-11 18:54:45 +00:00
|
|
|
continue;
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
2010-05-11 18:54:45 +00:00
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-13 20:43:17 +00:00
|
|
|
DEBUG(dbgs() << "Allocating %reg" << VirtReg << " from " << RC->getName()
|
2010-05-11 18:54:45 +00:00
|
|
|
<< " candidate=" << TRI->getName(BestReg) << "\n");
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// Try to extend the working set for RC if there were any disabled registers.
|
2010-05-17 02:49:15 +00:00
|
|
|
if (hasDisabled && (!BestReg || BestCost >= SpillCost)) {
|
2010-05-11 18:54:45 +00:00
|
|
|
for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
|
|
|
|
unsigned PhysReg = *I;
|
|
|
|
if (PhysRegState[PhysReg] != regDisabled || UsedInInstr.test(PhysReg))
|
|
|
|
continue;
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// Calculate the cost of bringing PhysReg into the working set.
|
|
|
|
unsigned Cost=0;
|
|
|
|
bool Impossible = false;
|
|
|
|
for (const unsigned *AS = TRI->getAliasSet(PhysReg);
|
|
|
|
unsigned Alias = *AS; ++AS) {
|
|
|
|
if (UsedInInstr.test(Alias)) {
|
|
|
|
Impossible = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
switch (PhysRegState[Alias]) {
|
|
|
|
case regDisabled:
|
|
|
|
break;
|
|
|
|
case regReserved:
|
|
|
|
Impossible = true;
|
|
|
|
break;
|
|
|
|
case regFree:
|
|
|
|
Cost++;
|
|
|
|
break;
|
|
|
|
default:
|
2010-05-17 02:49:15 +00:00
|
|
|
Cost += SpillCost;
|
2010-05-11 18:54:45 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (Impossible) continue;
|
2010-05-13 20:43:17 +00:00
|
|
|
DEBUG(dbgs() << "- candidate " << TRI->getName(PhysReg)
|
2010-05-11 18:54:45 +00:00
|
|
|
<< " cost=" << Cost << "\n");
|
|
|
|
if (!BestReg || Cost < BestCost) {
|
|
|
|
BestReg = PhysReg;
|
|
|
|
BestCost = Cost;
|
2010-05-17 02:49:15 +00:00
|
|
|
if (Cost < SpillCost) break;
|
2010-05-11 18:54:45 +00:00
|
|
|
}
|
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
if (BestReg) {
|
|
|
|
// BestCost is 0 when all aliases are already disabled.
|
|
|
|
if (BestCost) {
|
|
|
|
if (PhysRegState[BestReg] != regDisabled)
|
2010-05-17 02:07:32 +00:00
|
|
|
spillVirtReg(MI, PhysRegState[BestReg]);
|
2010-05-11 18:54:45 +00:00
|
|
|
else {
|
|
|
|
// Make sure all aliases are disabled.
|
|
|
|
for (const unsigned *AS = TRI->getAliasSet(BestReg);
|
|
|
|
unsigned Alias = *AS; ++AS) {
|
|
|
|
switch (PhysRegState[Alias]) {
|
|
|
|
case regDisabled:
|
|
|
|
continue;
|
|
|
|
case regFree:
|
|
|
|
PhysRegState[Alias] = regDisabled;
|
|
|
|
break;
|
|
|
|
default:
|
2010-05-17 02:07:32 +00:00
|
|
|
spillVirtReg(MI, PhysRegState[Alias]);
|
2010-05-11 18:54:45 +00:00
|
|
|
PhysRegState[Alias] = regDisabled;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
2010-05-17 02:07:29 +00:00
|
|
|
return assignVirtToPhysReg(LRE, BestReg);
|
2010-05-11 18:54:45 +00:00
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// Nothing we can do.
|
|
|
|
std::string msg;
|
|
|
|
raw_string_ostream Msg(msg);
|
|
|
|
Msg << "Ran out of registers during register allocation!";
|
|
|
|
if (MI->isInlineAsm()) {
|
|
|
|
Msg << "\nPlease check your inline asm statement for "
|
|
|
|
<< "invalid constraints:\n";
|
|
|
|
MI->print(Msg, TM);
|
|
|
|
}
|
|
|
|
report_fatal_error(Msg.str());
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
/// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
|
2010-05-17 03:26:09 +00:00
|
|
|
RAFast::LiveRegMap::iterator
|
|
|
|
RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum,
|
|
|
|
unsigned VirtReg, unsigned Hint) {
|
2010-05-11 18:54:45 +00:00
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
|
|
|
|
"Not a virtual register");
|
2010-05-17 02:49:15 +00:00
|
|
|
LiveRegMap::iterator LRI;
|
2010-05-17 02:07:29 +00:00
|
|
|
bool New;
|
2010-05-17 02:49:15 +00:00
|
|
|
tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
|
|
|
|
LiveReg &LR = LRI->second;
|
2010-05-17 04:50:57 +00:00
|
|
|
if (New) {
|
|
|
|
// If there is no hint, peek at the only use of this register.
|
|
|
|
if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
|
|
|
|
MRI->hasOneNonDBGUse(VirtReg)) {
|
|
|
|
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
|
|
|
|
// It's a copy, use the destination register as a hint.
|
|
|
|
if (TII->isMoveInstr(*MRI->use_nodbg_begin(VirtReg),
|
|
|
|
SrcReg, DstReg, SrcSubReg, DstSubReg))
|
|
|
|
Hint = DstReg;
|
|
|
|
}
|
2010-05-17 02:49:15 +00:00
|
|
|
allocVirtReg(MI, *LRI, Hint);
|
2010-05-17 04:50:57 +00:00
|
|
|
} else
|
2010-05-17 02:07:29 +00:00
|
|
|
addKillFlag(LR); // Kill before redefine.
|
|
|
|
assert(LR.PhysReg && "Register not assigned");
|
2010-05-11 23:24:47 +00:00
|
|
|
LR.LastUse = MI;
|
|
|
|
LR.LastOpNum = OpNum;
|
|
|
|
LR.Dirty = true;
|
|
|
|
UsedInInstr.set(LR.PhysReg);
|
2010-05-17 03:26:09 +00:00
|
|
|
return LRI;
|
2010-05-11 18:54:45 +00:00
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
/// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
|
2010-05-17 03:26:09 +00:00
|
|
|
RAFast::LiveRegMap::iterator
|
|
|
|
RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum,
|
|
|
|
unsigned VirtReg, unsigned Hint) {
|
2010-05-11 18:54:45 +00:00
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
|
|
|
|
"Not a virtual register");
|
2010-05-17 02:49:15 +00:00
|
|
|
LiveRegMap::iterator LRI;
|
2010-05-17 02:07:29 +00:00
|
|
|
bool New;
|
2010-05-17 02:49:15 +00:00
|
|
|
tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
|
|
|
|
LiveReg &LR = LRI->second;
|
2010-05-17 03:26:06 +00:00
|
|
|
MachineOperand &MO = MI->getOperand(OpNum);
|
2010-05-17 02:07:29 +00:00
|
|
|
if (New) {
|
2010-05-17 02:49:15 +00:00
|
|
|
allocVirtReg(MI, *LRI, Hint);
|
2010-05-13 00:19:43 +00:00
|
|
|
const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
|
2010-05-11 18:54:45 +00:00
|
|
|
int FrameIndex = getStackSpaceFor(VirtReg, RC);
|
2010-05-13 20:43:17 +00:00
|
|
|
DEBUG(dbgs() << "Reloading %reg" << VirtReg << " into "
|
2010-05-17 02:07:29 +00:00
|
|
|
<< TRI->getName(LR.PhysReg) << "\n");
|
|
|
|
TII->loadRegFromStackSlot(*MBB, MI, LR.PhysReg, FrameIndex, RC, TRI);
|
2010-05-11 18:54:45 +00:00
|
|
|
++NumLoads;
|
2010-05-17 02:07:29 +00:00
|
|
|
} else if (LR.Dirty) {
|
2010-05-15 06:09:08 +00:00
|
|
|
if (isLastUseOfLocalReg(MO)) {
|
|
|
|
DEBUG(dbgs() << "Killing last use: " << MO << "\n");
|
|
|
|
MO.setIsKill();
|
|
|
|
} else if (MO.isKill()) {
|
|
|
|
DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n");
|
|
|
|
MO.setIsKill(false);
|
|
|
|
}
|
2010-05-17 03:26:06 +00:00
|
|
|
} else if (MO.isKill()) {
|
|
|
|
// We must remove kill flags from uses of reloaded registers because the
|
|
|
|
// register would be killed immediately, and there might be a second use:
|
|
|
|
// %foo = OR %x<kill>, %x
|
|
|
|
// This would cause a second reload of %x into a different register.
|
|
|
|
DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n");
|
|
|
|
MO.setIsKill(false);
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
2010-05-17 02:07:29 +00:00
|
|
|
assert(LR.PhysReg && "Register not assigned");
|
2010-05-11 23:24:47 +00:00
|
|
|
LR.LastUse = MI;
|
|
|
|
LR.LastOpNum = OpNum;
|
|
|
|
UsedInInstr.set(LR.PhysReg);
|
2010-05-17 03:26:09 +00:00
|
|
|
return LRI;
|
2010-05-11 18:54:45 +00:00
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// setPhysReg - Change MO the refer the PhysReg, considering subregs.
|
2010-05-17 02:49:21 +00:00
|
|
|
// This may invalidate MO if it is necessary to add implicit kills for a
|
|
|
|
// superregister.
|
|
|
|
// Return tru if MO kills its register.
|
|
|
|
bool RAFast::setPhysReg(MachineOperand &MO, unsigned PhysReg) {
|
|
|
|
if (!MO.getSubReg()) {
|
2010-05-11 18:54:45 +00:00
|
|
|
MO.setReg(PhysReg);
|
2010-05-17 02:49:21 +00:00
|
|
|
return MO.isKill() || MO.isDead();
|
|
|
|
}
|
|
|
|
|
|
|
|
// Handle subregister index.
|
|
|
|
MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
|
|
|
|
MO.setSubReg(0);
|
|
|
|
if (MO.isUse()) {
|
|
|
|
if (MO.isKill()) {
|
|
|
|
MO.getParent()->addRegisterKilled(PhysReg, TRI, true);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
// A subregister def implicitly defines the whole physreg.
|
|
|
|
if (MO.isDead()) {
|
|
|
|
MO.getParent()->addRegisterDead(PhysReg, TRI, true);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
MO.getParent()->addRegisterDefined(PhysReg, TRI);
|
|
|
|
return false;
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-17 02:07:22 +00:00
|
|
|
void RAFast::AllocateBasicBlock() {
|
|
|
|
DEBUG(dbgs() << "\nAllocating " << *MBB);
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
PhysRegState.assign(TRI->getNumRegs(), regDisabled);
|
2010-05-11 23:24:45 +00:00
|
|
|
assert(LiveVirtRegs.empty() && "Mapping not cleared form last block?");
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-17 02:07:22 +00:00
|
|
|
MachineBasicBlock::iterator MII = MBB->begin();
|
2010-05-11 18:54:45 +00:00
|
|
|
|
|
|
|
// Add live-in registers as live.
|
2010-05-17 02:07:22 +00:00
|
|
|
for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
|
|
|
|
E = MBB->livein_end(); I != E; ++I)
|
|
|
|
definePhysReg(MII, *I, regReserved);
|
2010-05-11 18:54:45 +00:00
|
|
|
|
2010-05-17 03:26:06 +00:00
|
|
|
SmallVector<unsigned, 8> PhysECs;
|
2010-05-14 04:30:51 +00:00
|
|
|
SmallVector<MachineInstr*, 32> Coalesced;
|
2010-04-21 18:02:42 +00:00
|
|
|
|
|
|
|
// Otherwise, sequentially allocate each instruction in the MBB.
|
2010-05-17 02:07:22 +00:00
|
|
|
while (MII != MBB->end()) {
|
2010-04-21 18:02:42 +00:00
|
|
|
MachineInstr *MI = MII++;
|
|
|
|
const TargetInstrDesc &TID = MI->getDesc();
|
|
|
|
DEBUG({
|
2010-05-13 20:43:17 +00:00
|
|
|
dbgs() << "\n>> " << *MI << "Regs:";
|
2010-05-11 18:54:45 +00:00
|
|
|
for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
|
|
|
|
if (PhysRegState[Reg] == regDisabled) continue;
|
|
|
|
dbgs() << " " << TRI->getName(Reg);
|
|
|
|
switch(PhysRegState[Reg]) {
|
|
|
|
case regFree:
|
|
|
|
break;
|
|
|
|
case regReserved:
|
2010-05-13 20:43:17 +00:00
|
|
|
dbgs() << "*";
|
2010-05-11 18:54:45 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dbgs() << "=%reg" << PhysRegState[Reg];
|
2010-05-11 23:24:47 +00:00
|
|
|
if (LiveVirtRegs[PhysRegState[Reg]].Dirty)
|
2010-05-11 18:54:45 +00:00
|
|
|
dbgs() << "*";
|
2010-05-11 23:24:45 +00:00
|
|
|
assert(LiveVirtRegs[PhysRegState[Reg]].PhysReg == Reg &&
|
2010-05-11 18:54:45 +00:00
|
|
|
"Bad inverse map");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
dbgs() << '\n';
|
2010-05-11 23:24:45 +00:00
|
|
|
// Check that LiveVirtRegs is the inverse.
|
|
|
|
for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
|
|
|
|
e = LiveVirtRegs.end(); i != e; ++i) {
|
2010-05-11 18:54:45 +00:00
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(i->first) &&
|
|
|
|
"Bad map key");
|
2010-05-11 23:24:45 +00:00
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(i->second.PhysReg) &&
|
2010-05-11 18:54:45 +00:00
|
|
|
"Bad map value");
|
2010-05-11 23:24:45 +00:00
|
|
|
assert(PhysRegState[i->second.PhysReg] == i->first &&
|
|
|
|
"Bad inverse map");
|
2010-05-11 18:54:45 +00:00
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
});
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// Debug values are not allowed to change codegen in any way.
|
|
|
|
if (MI->isDebugValue()) {
|
2010-04-21 18:02:42 +00:00
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
2010-05-11 18:54:45 +00:00
|
|
|
if (!MO.isReg()) continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
|
2010-05-17 02:49:15 +00:00
|
|
|
LiveRegMap::iterator LRI = LiveVirtRegs.find(Reg);
|
|
|
|
if (LRI != LiveVirtRegs.end())
|
|
|
|
setPhysReg(MO, LRI->second.PhysReg);
|
2010-05-11 23:24:45 +00:00
|
|
|
else
|
|
|
|
MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry!
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
2010-05-11 18:54:45 +00:00
|
|
|
// Next instruction.
|
|
|
|
continue;
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-13 00:19:43 +00:00
|
|
|
// If this is a copy, we may be able to coalesce.
|
|
|
|
unsigned CopySrc, CopyDst, CopySrcSub, CopyDstSub;
|
|
|
|
if (!TII->isMoveInstr(*MI, CopySrc, CopyDst, CopySrcSub, CopyDstSub))
|
|
|
|
CopySrc = CopyDst = 0;
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// Track registers used by instruction.
|
|
|
|
UsedInInstr.reset();
|
2010-05-17 03:26:06 +00:00
|
|
|
PhysECs.clear();
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// First scan.
|
|
|
|
// Mark physreg uses and early clobbers as used.
|
2010-05-14 21:55:52 +00:00
|
|
|
// Find the end of the virtreg operands
|
|
|
|
unsigned VirtOpEnd = 0;
|
2010-05-11 18:54:45 +00:00
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
2010-04-21 18:02:42 +00:00
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
2010-05-11 18:54:45 +00:00
|
|
|
if (!MO.isReg()) continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
2010-05-14 21:55:52 +00:00
|
|
|
if (!Reg) continue;
|
|
|
|
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
|
|
|
VirtOpEnd = i+1;
|
|
|
|
continue;
|
|
|
|
}
|
2010-05-14 22:02:56 +00:00
|
|
|
if (!Allocatable.test(Reg)) continue;
|
2010-05-11 18:54:45 +00:00
|
|
|
if (MO.isUse()) {
|
2010-05-14 18:03:25 +00:00
|
|
|
usePhysReg(MO);
|
2010-05-11 18:54:45 +00:00
|
|
|
} else if (MO.isEarlyClobber()) {
|
2010-05-17 02:07:22 +00:00
|
|
|
definePhysReg(MI, Reg, MO.isDead() ? regFree : regReserved);
|
2010-05-17 03:26:06 +00:00
|
|
|
PhysECs.push_back(Reg);
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// Second scan.
|
|
|
|
// Allocate virtreg uses and early clobbers.
|
|
|
|
// Collect VirtKills
|
2010-05-14 21:55:52 +00:00
|
|
|
for (unsigned i = 0; i != VirtOpEnd; ++i) {
|
2010-04-21 18:02:42 +00:00
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
2010-05-11 18:54:45 +00:00
|
|
|
if (!MO.isReg()) continue;
|
2010-04-21 18:02:42 +00:00
|
|
|
unsigned Reg = MO.getReg();
|
2010-05-11 18:54:45 +00:00
|
|
|
if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
|
|
|
|
if (MO.isUse()) {
|
2010-05-17 03:26:09 +00:00
|
|
|
LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst);
|
|
|
|
unsigned PhysReg = LRI->second.PhysReg;
|
2010-05-14 04:30:51 +00:00
|
|
|
CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;
|
2010-05-17 02:49:21 +00:00
|
|
|
if (setPhysReg(MO, PhysReg))
|
2010-05-17 03:26:09 +00:00
|
|
|
killVirtReg(LRI);
|
2010-05-11 18:54:45 +00:00
|
|
|
} else if (MO.isEarlyClobber()) {
|
2010-05-17 03:26:09 +00:00
|
|
|
LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
|
|
|
|
unsigned PhysReg = LRI->second.PhysReg;
|
2010-05-11 18:54:45 +00:00
|
|
|
setPhysReg(MO, PhysReg);
|
2010-05-17 03:26:06 +00:00
|
|
|
PhysECs.push_back(PhysReg);
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-05-13 00:19:43 +00:00
|
|
|
MRI->addPhysRegsUsed(UsedInInstr);
|
2010-05-11 20:30:28 +00:00
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// Track registers defined by instruction - early clobbers at this point.
|
|
|
|
UsedInInstr.reset();
|
2010-05-17 03:26:06 +00:00
|
|
|
for (unsigned i = 0, e = PhysECs.size(); i != e; ++i) {
|
|
|
|
unsigned PhysReg = PhysECs[i];
|
2010-05-11 18:54:45 +00:00
|
|
|
UsedInInstr.set(PhysReg);
|
|
|
|
for (const unsigned *AS = TRI->getAliasSet(PhysReg);
|
|
|
|
unsigned Alias = *AS; ++AS)
|
|
|
|
UsedInInstr.set(Alias);
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-17 02:49:18 +00:00
|
|
|
unsigned DefOpEnd = MI->getNumOperands();
|
|
|
|
if (TID.isCall()) {
|
|
|
|
// Spill all virtregs before a call. This serves two purposes: 1. If an
|
|
|
|
// exception is thrown, the landing pad is going to expect to find registers
|
|
|
|
// in their spill slots, and 2. we don't have to wade through all the
|
|
|
|
// <imp-def> operands on the call instruction.
|
|
|
|
DefOpEnd = VirtOpEnd;
|
|
|
|
DEBUG(dbgs() << " Spilling remaining registers before call.\n");
|
|
|
|
spillAll(MI);
|
|
|
|
}
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// Third scan.
|
|
|
|
// Allocate defs and collect dead defs.
|
2010-05-17 02:49:18 +00:00
|
|
|
for (unsigned i = 0; i != DefOpEnd; ++i) {
|
2010-04-21 18:02:42 +00:00
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
2010-05-11 18:54:45 +00:00
|
|
|
if (!MO.isReg() || !MO.isDef() || !MO.getReg()) continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
2010-05-14 22:02:56 +00:00
|
|
|
if (!Allocatable.test(Reg)) continue;
|
2010-05-17 02:07:22 +00:00
|
|
|
definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
|
|
|
|
regFree : regReserved);
|
2010-05-11 18:54:45 +00:00
|
|
|
continue;
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
2010-05-17 03:26:09 +00:00
|
|
|
LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc);
|
|
|
|
unsigned PhysReg = LRI->second.PhysReg;
|
2010-05-17 02:49:21 +00:00
|
|
|
if (setPhysReg(MO, PhysReg)) {
|
2010-05-17 03:26:09 +00:00
|
|
|
killVirtReg(LRI);
|
2010-05-14 04:30:51 +00:00
|
|
|
CopyDst = 0; // cancel coalescing;
|
|
|
|
} else
|
|
|
|
CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0;
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-13 00:19:43 +00:00
|
|
|
MRI->addPhysRegsUsed(UsedInInstr);
|
2010-05-13 20:43:17 +00:00
|
|
|
|
2010-05-14 04:30:51 +00:00
|
|
|
if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) {
|
|
|
|
DEBUG(dbgs() << "-- coalescing: " << *MI);
|
|
|
|
Coalesced.push_back(MI);
|
|
|
|
} else {
|
|
|
|
DEBUG(dbgs() << "<< " << *MI);
|
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// Spill all physical registers holding virtual registers now.
|
2010-05-17 02:07:32 +00:00
|
|
|
DEBUG(dbgs() << "Spilling live registers at end of block.\n");
|
|
|
|
spillAll(MBB->getFirstTerminator());
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-14 04:30:51 +00:00
|
|
|
// Erase all the coalesced copies. We are delaying it until now because
|
2010-05-17 02:07:32 +00:00
|
|
|
// LiveVirtRegs might refer to the instrs.
|
2010-05-14 04:30:51 +00:00
|
|
|
for (unsigned i = 0, e = Coalesced.size(); i != e; ++i)
|
2010-05-17 02:07:22 +00:00
|
|
|
MBB->erase(Coalesced[i]);
|
2010-05-14 21:55:50 +00:00
|
|
|
NumCopies += Coalesced.size();
|
2010-05-14 04:30:51 +00:00
|
|
|
|
2010-05-17 02:07:22 +00:00
|
|
|
DEBUG(MBB->dump());
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// runOnMachineFunction - Register allocate the whole function
|
|
|
|
///
|
|
|
|
bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
|
2010-05-13 20:43:17 +00:00
|
|
|
DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n"
|
|
|
|
<< "********** Function: "
|
|
|
|
<< ((Value*)Fn.getFunction())->getName() << '\n');
|
2010-05-14 20:28:32 +00:00
|
|
|
if (VerifyFastRegalloc)
|
2010-05-14 21:55:44 +00:00
|
|
|
Fn.verify(this, true);
|
2010-04-21 18:02:42 +00:00
|
|
|
MF = &Fn;
|
2010-05-13 00:19:43 +00:00
|
|
|
MRI = &MF->getRegInfo();
|
2010-04-21 18:02:42 +00:00
|
|
|
TM = &Fn.getTarget();
|
|
|
|
TRI = TM->getRegisterInfo();
|
|
|
|
TII = TM->getInstrInfo();
|
|
|
|
|
|
|
|
UsedInInstr.resize(TRI->getNumRegs());
|
2010-05-14 22:02:56 +00:00
|
|
|
Allocatable = TRI->getAllocatableSet(*MF);
|
2010-04-21 18:02:42 +00:00
|
|
|
|
|
|
|
// initialize the virtual->physical register map to have a 'null'
|
|
|
|
// mapping for all virtual registers
|
2010-05-13 00:19:43 +00:00
|
|
|
unsigned LastVirtReg = MRI->getLastVirtReg();
|
2010-04-21 18:02:42 +00:00
|
|
|
StackSlotForVirtReg.grow(LastVirtReg);
|
|
|
|
|
|
|
|
// Loop over all of the basic blocks, eliminating virtual register references
|
2010-05-17 02:07:22 +00:00
|
|
|
for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end();
|
|
|
|
MBBi != MBBe; ++MBBi) {
|
|
|
|
MBB = &*MBBi;
|
|
|
|
AllocateBasicBlock();
|
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-11 20:30:28 +00:00
|
|
|
// Make sure the set of used physregs is closed under subreg operations.
|
2010-05-13 00:19:43 +00:00
|
|
|
MRI->closePhysRegsUsed(*TRI);
|
2010-05-11 20:30:28 +00:00
|
|
|
|
2010-04-21 18:02:42 +00:00
|
|
|
StackSlotForVirtReg.clear();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
FunctionPass *llvm::createFastRegisterAllocator() {
|
|
|
|
return new RAFast();
|
|
|
|
}
|