llvm/test/CodeGen/Blackfin/add-overflow.ll

; RUN: llc < %s -march=bfin -verify-machineinstrs > %t

	type { i24, i1 }		; type %0

define i1 @func2(i24 zeroext %v1, i24 zeroext %v2) nounwind {
entry:
	%t = call %0 @llvm.uadd.with.overflow.i24(i24 %v1, i24 %v2)		; <%0> [#uses=1]
	%obit = extractvalue %0 %t, 1		; <i1> [#uses=1]
	br i1 %obit, label %carry, label %normal

normal:		; preds = %entry
	ret i1 true

carry:		; preds = %entry
	ret i1 false
}

declare %0 @llvm.uadd.with.overflow.i24(i24, i24) nounwind
Eliminate more uses of llvm-as and llvm-dis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8 2009-09-09 00:09:15 +00:00			`; RUN: llc < %s -march=bfin -verify-machineinstrs > %t`
Analog Devices Blackfin back-end. Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77897 91177308-0d34-0410-b5e6-96231b3b80d8 2009-08-02 17:32:10 +00:00
			`type { i24, i1 } ; type %0`

			`define i1 @func2(i24 zeroext %v1, i24 zeroext %v2) nounwind {`
			`entry:`
			`%t = call %0 @llvm.uadd.with.overflow.i24(i24 %v1, i24 %v2) ; <%0> [#uses=1]`
			`%obit = extractvalue %0 %t, 1 ; <i1> [#uses=1]`
			`br i1 %obit, label %carry, label %normal`

			`normal: ; preds = %entry`
			`ret i1 true`

			`carry: ; preds = %entry`
			`ret i1 false`
			`}`

			`declare %0 @llvm.uadd.with.overflow.i24(i24, i24) nounwind`