RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-11-25 20:59:51 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
c4fea3594f
llvm/test/CodeGen/R600/fabs.ll

55 lines
1.7 KiB
LLVM
Raw Normal View History

DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free This commit also implements these functions for R600 and removes a test case that was relying on the buggy behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187007 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 23:55:03 +00:00
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
R600/SI: Use -verify-machineinstrs for most tests We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-10 17:11:46 +00:00
; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 21:25:42 +00:00
DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free This commit also implements these functions for R600 and removes a test case that was relying on the buggy behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187007 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 23:55:03 +00:00
; DAGCombiner will transform:
; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))
; unless isFabsFree returns true
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 21:25:42 +00:00
R600: Expand vector FABS NOTE: This is a candidate for the 3.4 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195881 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 21:23:39 +00:00
; R600-CHECK-LABEL: @fabs_free
DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free This commit also implements these functions for R600 and removes a test case that was relying on the buggy behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187007 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 23:55:03 +00:00
; R600-CHECK-NOT: AND
; R600-CHECK: |PV.{{[XYZW]}}|
R600: Expand vector FABS NOTE: This is a candidate for the 3.4 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195881 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 21:23:39 +00:00
; SI-CHECK-LABEL: @fabs_free
R600/SI: Fix fneg for 0.0 V_ADD_F32 with source modifier does not produce -0.0 for this. Just manipulate the sign bit directly instead. Also add a pattern for (fneg (fabs ...)). Fixes a bunch of bit encoding piglit tests with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200743 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 07:12:38 +00:00
; SI-CHECK: V_AND_B32
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 21:25:42 +00:00
DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free This commit also implements these functions for R600 and removes a test case that was relying on the buggy behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187007 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 23:55:03 +00:00
define void @fabs_free(float addrspace(1)* %out, i32 %in) {
entry:
%0 = bitcast i32 %in to float
%1 = call float @fabs(float %0)
store float %1, float addrspace(1)* %out
ret void
}
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 21:25:42 +00:00
R600: Expand vector FABS NOTE: This is a candidate for the 3.4 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195881 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 21:23:39 +00:00
; R600-CHECK-LABEL: @fabs_v2
; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
; SI-CHECK-LABEL: @fabs_v2
R600/SI: Fix fneg for 0.0 V_ADD_F32 with source modifier does not produce -0.0 for this. Just manipulate the sign bit directly instead. Also add a pattern for (fneg (fabs ...)). Fixes a bunch of bit encoding piglit tests with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200743 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 07:12:38 +00:00
; SI-CHECK: V_AND_B32
; SI-CHECK: V_AND_B32
R600: Expand vector FABS NOTE: This is a candidate for the 3.4 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195881 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 21:23:39 +00:00
define void @fabs_v2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
entry:
%0 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
store <2 x float> %0, <2 x float> addrspace(1)* %out
ret void
}
; R600-CHECK-LABEL: @fabs_v4
; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
; SI-CHECK-LABEL: @fabs_v4
R600/SI: Fix fneg for 0.0 V_ADD_F32 with source modifier does not produce -0.0 for this. Just manipulate the sign bit directly instead. Also add a pattern for (fneg (fabs ...)). Fixes a bunch of bit encoding piglit tests with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200743 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 07:12:38 +00:00
; SI-CHECK: V_AND_B32
; SI-CHECK: V_AND_B32
; SI-CHECK: V_AND_B32
; SI-CHECK: V_AND_B32
R600: Expand vector FABS NOTE: This is a candidate for the 3.4 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195881 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 21:23:39 +00:00
define void @fabs_v4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
entry:
%0 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
store <4 x float> %0, <4 x float> addrspace(1)* %out
ret void
}
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 21:25:42 +00:00
declare float @fabs(float ) readnone
R600: Expand vector FABS NOTE: This is a candidate for the 3.4 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195881 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 21:23:39 +00:00
declare <2 x float> @llvm.fabs.v2f32(<2 x float> ) readnone
declare <4 x float> @llvm.fabs.v4f32(<4 x float> ) readnone
Reference in New Issue Copy Permalink