llvm/test/CodeGen/X86/widen_shuffle-1.ll

; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t -f

; widening shuffle v3float and then a add

define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
entry:
	%x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 1, i32 2>
	%val = fadd <3 x float> %x, %src2;
	store <3 x float> %val, <3 x float>* %dst.addr
	ret void
}
Added some basic test cases for r61209 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61210 91177308-0d34-0410-b5e6-96231b3b80d8 2008-12-18 20:05:58 +00:00			`; RUN: llvm-as < %s \| llc -march=x86 -mattr=+sse42 -disable-mmx -o %t -f`

			`; widening shuffle v3float and then a add`

			`define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {`
			`entry:`
			`%x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 1, i32 2>`
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8 2009-06-04 22:49:04 +00:00			`%val = fadd <3 x float> %x, %src2;`
Added some basic test cases for r61209 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61210 91177308-0d34-0410-b5e6-96231b3b80d8 2008-12-18 20:05:58 +00:00			`store <3 x float> %val, <3 x float>* %dst.addr`
			`ret void`
			`}`