llvm/test/CodeGen/R600/selectcc-cnde-int.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s

;CHECK-NOT: SETE_INT
;CHECK: CNDE_INT {{\*?}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, literal.x,
;CHECK-NEXT: 2
define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
  %1 = load i32 addrspace(1)* %in
  %2 = icmp eq i32 %1, 0
  %3 = select i1 %2, i32 1, i32 2
  store i32 %3, i32 addrspace(1)* %out
  ret void
}
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8 2012-12-11 21:25:42 +00:00			`;RUN: llc < %s -march=r600 -mcpu=redwood \| FileCheck %s`

			`;CHECK-NOT: SETE_INT`
R600: Non vector only instruction can be scheduled on trans unit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189980 91177308-0d34-0410-b5e6-96231b3b80d8 2013-09-04 19:53:46 +00:00			`;CHECK: CNDE_INT {{\*?}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, literal.x,`
R600: Prettier asmPrint of Alu git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-02 21:52:30 +00:00			`;CHECK-NEXT: 2`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8 2012-12-11 21:25:42 +00:00			`define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {`
			`%1 = load i32 addrspace(1)* %in`
			`%2 = icmp eq i32 %1, 0`
			`%3 = select i1 %2, i32 1, i32 2`
			`store i32 %3, i32 addrspace(1)* %out`
			`ret void`
			`}`