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Generate the SparcV8 code emitter from .td files

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17000 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-10-14 21:57:19 +00:00
parent 17187e936a
commit 009d3f400c
2 changed files with 10 additions and 2 deletions
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6
lib/Target/Sparc/Makefile
View File

@ -16,7 +16,7 @@ TDFILE := $(SourceDir)/SparcV8.td
# Make sure that tblgen is run, first thing. # Make sure that tblgen is run, first thing.
$(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \ $(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \ SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
SparcV8GenInstrInfo.inc SparcV8GenInstrInfo.inc SparcV8GenCodeEmitter.inc
SparcV8GenRegisterNames.inc:: $(TDFILES) $(TBLGEN) SparcV8GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td register names with tblgen" @echo "Building SparcV8.td register names with tblgen"
@ -38,5 +38,9 @@ SparcV8GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td instruction information with tblgen" @echo "Building SparcV8.td instruction information with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-desc -o $@ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-desc -o $@
SparcV8GenCodeEmitter.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td code emitter with tblgen"
$(VERB) $(TBLGEN) -I $(SourceDir) $(TDFILE) -gen-emitter -o $@
clean:: clean::
$(VERB) rm -f *.inc $(VERB) rm -f *.inc

6
lib/Target/SparcV8/Makefile
View File

@ -16,7 +16,7 @@ TDFILE := $(SourceDir)/SparcV8.td
# Make sure that tblgen is run, first thing. # Make sure that tblgen is run, first thing.
$(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \ $(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \ SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
SparcV8GenInstrInfo.inc SparcV8GenInstrInfo.inc SparcV8GenCodeEmitter.inc
SparcV8GenRegisterNames.inc:: $(TDFILES) $(TBLGEN) SparcV8GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td register names with tblgen" @echo "Building SparcV8.td register names with tblgen"
@ -38,5 +38,9 @@ SparcV8GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td instruction information with tblgen" @echo "Building SparcV8.td instruction information with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-desc -o $@ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-desc -o $@
SparcV8GenCodeEmitter.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td code emitter with tblgen"
$(VERB) $(TBLGEN) -I $(SourceDir) $(TDFILE) -gen-emitter -o $@
clean:: clean::
$(VERB) rm -f *.inc $(VERB) rm -f *.inc