R600/SI: add SETO/SETUO patterns

6 more piglit tests.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178145 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christian Konig 2013-03-27 15:27:31 +00:00
parent 2b393fb134
commit 00b3b5fbf4
3 changed files with 40 additions and 0 deletions

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@ -1590,4 +1590,18 @@ defm : SI_INDIRECT_Pattern <VReg_128, v4f32, SI_INDIRECT_DST_V4>;
defm : SI_INDIRECT_Pattern <VReg_256, v8f32, SI_INDIRECT_DST_V8>;
defm : SI_INDIRECT_Pattern <VReg_512, v16f32, SI_INDIRECT_DST_V16>;
/********** =============== **********/
/********** Conditions **********/
/********** =============== **********/
def : Pat<
(i1 (setcc f32:$src0, f32:$src1, SETO)),
(V_CMP_O_F32_e64 f32:$src0, f32:$src1)
>;
def : Pat<
(i1 (setcc f32:$src0, f32:$src1, SETUO)),
(V_CMP_U_F32_e64 f32:$src0, f32:$src1)
>;
} // End isSI predicate

13
test/CodeGen/R600/seto.ll Normal file
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@ -0,0 +1,13 @@
;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
;CHECK: V_CMP_O_F32_e64 SGPR0_SGPR1, VGPR0, VGPR0, 0, 0, 0, 0
define void @main(float %p) {
main_body:
%c = fcmp oeq float %p, %p
%r = select i1 %c, float 1.000000e+00, float 0.000000e+00
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %r, float %r, float %r, float %r)
ret void
}
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

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@ -0,0 +1,13 @@
;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
;CHECK: V_CMP_U_F32_e64 SGPR0_SGPR1, VGPR0, VGPR0, 0, 0, 0, 0
define void @main(float %p) {
main_body:
%c = fcmp une float %p, %p
%r = select i1 %c, float 1.000000e+00, float 0.000000e+00
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %r, float %r, float %r, float %r)
ret void
}
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)