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Minor cleanup to all the switches after MatchInstructionImpl in all the AsmParsers.

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Make sure they all have llvm_unreachable on the default path out of the switch. Remove unnecessary "default: break". Remove a 'return' after unreachable. Fix some indentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225114 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2015-01-03 08:16:34 +00:00
parent 2717b066cc
commit 00d70e98f0
8 changed files with 19 additions and 28 deletions
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1
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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@ -3927,7 +3927,6 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
}
llvm_unreachable("Implement any new match types added!");
return true;
}
/// ParseDirective parses the arm specific directives

1
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -8575,7 +8575,6 @@ bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
MatchingInlineAsm);
switch (MatchResult) {
default: break;
case Match_Success:
// Context sensitive operand constraints aren't handled by the matcher,
// so check them here.

5
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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@ -1852,8 +1852,6 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
switch (MatchResult) {
default:
break;
case Match_Success: {
if (processInstruction(Inst, IDLoc, Instructions))
return true;
@ -1882,7 +1880,8 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_RequiresDifferentSrcAndDst:
return Error(IDLoc, "source and destination must be different");
}
return true;
llvm_unreachable("Implement any new match types added!");
}
void MipsAsmParser::warnIfAssemblerTemporary(int RegIndex, SMLoc Loc) {

3
lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
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@ -1053,7 +1053,6 @@ bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
MCInst Inst;
switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
default: break;
case Match_Success:
// Post-process instructions (typically extended mnemonics)
ProcessInstruction(Inst, Operands);
@ -1063,7 +1062,7 @@ bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_MissingFeature:
return Error(IDLoc, "instruction use requires an option to be enabled");
case Match_MnemonicFail:
return Error(IDLoc, "unrecognized instruction mnemonic");
return Error(IDLoc, "unrecognized instruction mnemonic");
case Match_InvalidOperand: {
SMLoc ErrorLoc = IDLoc;
if (ErrorInfo != ~0ULL) {

29
lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp
View File

@ -163,23 +163,22 @@ bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
MCInst Inst;
switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
default: break;
case Match_Success:
Inst.setLoc(IDLoc);
Out.EmitInstruction(Inst, STI);
return false;
case Match_MissingFeature:
return Error(IDLoc, "instruction use requires an option to be enabled");
case Match_MnemonicFail:
return Error(IDLoc, "unrecognized instruction mnemonic");
case Match_InvalidOperand: {
if (ErrorInfo != ~0ULL) {
if (ErrorInfo >= Operands.size())
return Error(IDLoc, "too few operands for instruction");
case Match_Success:
Inst.setLoc(IDLoc);
Out.EmitInstruction(Inst, STI);
return false;
case Match_MissingFeature:
return Error(IDLoc, "instruction use requires an option to be enabled");
case Match_MnemonicFail:
return Error(IDLoc, "unrecognized instruction mnemonic");
case Match_InvalidOperand: {
if (ErrorInfo != ~0ULL) {
if (ErrorInfo >= Operands.size())
return Error(IDLoc, "too few operands for instruction");
}
return Error(IDLoc, "invalid operand for instruction");
}
return Error(IDLoc, "invalid operand for instruction");
}
}
llvm_unreachable("Implement any new match types added!");
}

5
lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
View File

@ -393,9 +393,6 @@ bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
MatchingInlineAsm);
switch (MatchResult) {
default:
break;
case Match_Success: {
Inst.setLoc(IDLoc);
Out.EmitInstruction(Inst, STI);
@ -422,7 +419,7 @@ bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_MnemonicFail:
return Error(IDLoc, "invalid instruction mnemonic");
}
return true;
llvm_unreachable("Implement any new match types added!");
}
bool SparcAsmParser::

1
lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
View File

@ -685,7 +685,6 @@ bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
MatchingInlineAsm);
switch (MatchResult) {
default: break;
case Match_Success:
Inst.setLoc(IDLoc);
Out.EmitInstruction(Inst, STI);

2
lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -2432,7 +2432,7 @@ bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
switch (MatchInstructionImpl(Operands, Inst,
ErrorInfo, MatchingInlineAsm,
isParsingIntelSyntax())) {
default: break;
default: llvm_unreachable("Unexpected match result!");
case Match_Success:
// Some instructions need post-processing to, for example, tweak which
// encoding is selected. Loop on it while changes happen so the