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https://github.com/RPCSX/llvm.git
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convert cmp to use a multipattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115978 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
835580fc3a
commit
00e94baf4e
@ -600,25 +600,32 @@ class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
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// BinOpRR - Instructions like "add reg, reg, reg".
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class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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list<dag> pattern>
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: ITy<opcode, MRMDestReg, typeinfo,
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(outs typeinfo.RegClass:$dst),
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dag outlist, list<dag> pattern>
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: ITy<opcode, MRMDestReg, typeinfo, outlist,
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(ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
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mnemonic, "{$src2, $dst|$dst, $src2}", pattern>;
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mnemonic, "{$src2, $src1|$src1, $src2}", pattern>;
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// BinOpRR_R - Instructions like "add reg, reg, reg", where the pattern has
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// just a regclass (no eflags) as a result.
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class BinOpRR_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode>
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: BinOpRR<opcode, mnemonic, typeinfo,
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: BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
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[(set typeinfo.RegClass:$dst,
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(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
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// BinOpRR_F - Instructions like "cmp reg, Reg", where the pattern has
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// just a EFLAGS as a result.
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class BinOpRR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode>
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: BinOpRR<opcode, mnemonic, typeinfo, (outs),
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[(set EFLAGS,
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(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
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// BinOpRR_RF - Instructions like "add reg, reg, reg", where the pattern has
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// both a regclass and EFLAGS as a result.
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class BinOpRR_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode>
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: BinOpRR<opcode, mnemonic, typeinfo,
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: BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
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[(set typeinfo.RegClass:$dst, EFLAGS,
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(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
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@ -634,107 +641,160 @@ class BinOpRR_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
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// BinOpRM - Instructions like "add reg, reg, [mem]".
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class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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list<dag> pattern>
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: ITy<opcode, MRMSrcMem, typeinfo,
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(outs typeinfo.RegClass:$dst),
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dag outlist, list<dag> pattern>
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: ITy<opcode, MRMSrcMem, typeinfo, outlist,
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(ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
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mnemonic, "{$src2, $dst|$dst, $src2}", pattern>;
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mnemonic, "{$src2, $src1|$src1, $src2}", pattern>;
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// BinOpRM_R - Instructions like "add reg, reg, [mem]".
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class BinOpRM_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode>
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: BinOpRM<opcode, mnemonic, typeinfo,
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: BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
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[(set typeinfo.RegClass:$dst,
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(opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
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// BinOpRM_F - Instructions like "cmp reg, [mem]".
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class BinOpRM_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode>
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: BinOpRM<opcode, mnemonic, typeinfo, (outs),
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[(set EFLAGS,
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(opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
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// BinOpRM_RF - Instructions like "add reg, reg, [mem]".
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class BinOpRM_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode>
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: BinOpRM<opcode, mnemonic, typeinfo,
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: BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
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[(set typeinfo.RegClass:$dst, EFLAGS,
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(opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
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// BinOpRI - Instructions like "add reg, reg, imm".
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class BinOpRI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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Format f, list<dag> pattern>
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: ITy<opcode, f, typeinfo,
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(outs typeinfo.RegClass:$dst),
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Format f, dag outlist, list<dag> pattern>
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: ITy<opcode, f, typeinfo, outlist,
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(ins typeinfo.RegClass:$src1, typeinfo.ImmOperand:$src2),
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mnemonic, "{$src2, $dst|$dst, $src2}", pattern> {
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mnemonic, "{$src2, $src1|$src1, $src2}", pattern> {
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let ImmT = typeinfo.ImmEncoding;
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}
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// BinOpRI_R - Instructions like "add reg, reg, imm".
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class BinOpRI_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode, Format f>
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: BinOpRI<opcode, mnemonic, typeinfo, f,
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: BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
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[(set typeinfo.RegClass:$dst,
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(opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
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// BinOpRI_F - Instructions like "cmp reg, imm".
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class BinOpRI_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode, Format f>
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: BinOpRI<opcode, mnemonic, typeinfo, f, (outs),
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[(set EFLAGS,
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(opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
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// BinOpRI_RF - Instructions like "add reg, reg, imm".
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class BinOpRI_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode, Format f>
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: BinOpRI<opcode, mnemonic, typeinfo, f,
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: BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
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[(set typeinfo.RegClass:$dst, EFLAGS,
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(opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
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// BinOpRI8 - Instructions like "add reg, reg, imm8".
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class BinOpRI8<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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Format f, list<dag> pattern>
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: ITy<opcode, f, typeinfo,
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(outs typeinfo.RegClass:$dst),
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Format f, dag outlist, list<dag> pattern>
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: ITy<opcode, f, typeinfo, outlist,
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(ins typeinfo.RegClass:$src1, typeinfo.Imm8Operand:$src2),
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mnemonic, "{$src2, $dst|$dst, $src2}", pattern> {
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mnemonic, "{$src2, $src1|$src1, $src2}", pattern> {
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let ImmT = Imm8; // Always 8-bit immediate.
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}
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// BinOpRI8_R - Instructions like "add reg, reg, imm8".
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class BinOpRI8_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode, Format f>
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: BinOpRI8<opcode, mnemonic, typeinfo, f,
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: BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
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[(set typeinfo.RegClass:$dst,
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(opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
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// BinOpRI8_F - Instructions like "cmp reg, imm8".
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class BinOpRI8_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode, Format f>
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: BinOpRI8<opcode, mnemonic, typeinfo, f, (outs),
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[(set EFLAGS,
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(opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
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// BinOpRI8_RF - Instructions like "add reg, reg, imm8".
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class BinOpRI8_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode, Format f>
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: BinOpRI8<opcode, mnemonic, typeinfo, f,
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: BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
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[(set typeinfo.RegClass:$dst, EFLAGS,
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(opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
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// BinOpMR - Instructions like "add [mem], reg".
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class BinOpMR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode>
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list<dag> pattern>
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: ITy<opcode, MRMDestMem, typeinfo,
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(outs), (ins typeinfo.MemOperand:$dst, typeinfo.RegClass:$src),
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mnemonic, "{$src, $dst|$dst, $src}",
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[(store (opnode (load addr:$dst), typeinfo.RegClass:$src), addr:$dst),
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(implicit EFLAGS)]>;
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mnemonic, "{$src, $dst|$dst, $src}", pattern>;
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// BinOpMR_RMW - Instructions like "add [mem], reg".
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class BinOpMR_RMW<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode>
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: BinOpMR<opcode, mnemonic, typeinfo,
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[(store (opnode (load addr:$dst), typeinfo.RegClass:$src), addr:$dst),
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(implicit EFLAGS)]>;
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// BinOpMR_F - Instructions like "cmp [mem], reg".
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class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode>
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: BinOpMR<opcode, mnemonic, typeinfo,
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[(set EFLAGS, (opnode (load addr:$dst), typeinfo.RegClass:$src))]>;
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// BinOpMI - Instructions like "add [mem], imm".
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class BinOpMI<string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode, Format f>
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Format f, list<dag> pattern>
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: ITy<0x80, f, typeinfo,
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(outs), (ins typeinfo.MemOperand:$dst, typeinfo.ImmOperand:$src),
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mnemonic, "{$src, $dst|$dst, $src}",
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[(store (opnode (typeinfo.VT (load addr:$dst)),
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typeinfo.ImmOperator:$src), addr:$dst),
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(implicit EFLAGS)]> {
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mnemonic, "{$src, $dst|$dst, $src}", pattern> {
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let ImmT = typeinfo.ImmEncoding;
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}
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// BinOpMI_RMW - Instructions like "add [mem], imm".
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class BinOpMI_RMW<string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode, Format f>
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: BinOpMI<mnemonic, typeinfo, f,
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[(store (opnode (typeinfo.VT (load addr:$dst)),
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typeinfo.ImmOperator:$src), addr:$dst),
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(implicit EFLAGS)]>;
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// BinOpMI_F - Instructions like "cmp [mem], imm".
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class BinOpMI_F<string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode, Format f>
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: BinOpMI<mnemonic, typeinfo, f,
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[(set EFLAGS, (opnode (typeinfo.VT (load addr:$dst)),
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typeinfo.ImmOperator:$src))]>;
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// BinOpMI8 - Instructions like "add [mem], imm8".
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class BinOpMI8<string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode, Format f>
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Format f, list<dag> pattern>
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: ITy<0x82, f, typeinfo,
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(outs), (ins typeinfo.MemOperand:$dst, typeinfo.Imm8Operand:$src),
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mnemonic, "{$src, $dst|$dst, $src}",
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[(store (opnode (load addr:$dst),
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typeinfo.Imm8Operator:$src), addr:$dst),
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(implicit EFLAGS)]> {
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mnemonic, "{$src, $dst|$dst, $src}", pattern> {
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let ImmT = Imm8; // Always 8-bit immediate.
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}
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// BinOpMI8_RMW - Instructions like "add [mem], imm8".
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class BinOpMI8_RMW<string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode, Format f>
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: BinOpMI8<mnemonic, typeinfo, f,
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[(store (opnode (load addr:$dst),
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typeinfo.Imm8Operator:$src), addr:$dst),
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(implicit EFLAGS)]>;
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// BinOpMI8_F - Instructions like "cmp [mem], imm8".
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class BinOpMI8_F<string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode, Format f>
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: BinOpMI8<mnemonic, typeinfo, f,
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[(set EFLAGS, (opnode (load addr:$dst),
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typeinfo.Imm8Operator:$src))]>;
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// BinOpAI - Instructions like "add %eax, %eax, imm".
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class BinOpAI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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Register areg>
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@ -788,19 +848,19 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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}
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} // Constraints = "$src1 = $dst"
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def #NAME#8mr : BinOpMR<BaseOpc, mnemonic, Xi8 , opnode>;
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def #NAME#16mr : BinOpMR<BaseOpc, mnemonic, Xi16, opnode>;
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def #NAME#32mr : BinOpMR<BaseOpc, mnemonic, Xi32, opnode>;
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def #NAME#64mr : BinOpMR<BaseOpc, mnemonic, Xi64, opnode>;
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def #NAME#8mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>;
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def #NAME#16mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>;
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def #NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>;
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def #NAME#64mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>;
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def #NAME#8mi : BinOpMI<mnemonic, Xi8 , opnode, MemMRM>;
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def #NAME#16mi : BinOpMI<mnemonic, Xi16, opnode, MemMRM>;
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def #NAME#32mi : BinOpMI<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi32 : BinOpMI<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#8mi : BinOpMI_RMW<mnemonic, Xi8 , opnode, MemMRM>;
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def #NAME#16mi : BinOpMI_RMW<mnemonic, Xi16, opnode, MemMRM>;
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def #NAME#32mi : BinOpMI_RMW<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi32 : BinOpMI_RMW<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#16mi8 : BinOpMI8<mnemonic, Xi16, opnode, MemMRM>;
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def #NAME#32mi8 : BinOpMI8<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi8 : BinOpMI8<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#16mi8 : BinOpMI8_RMW<mnemonic, Xi16, opnode, MemMRM>;
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def #NAME#32mi8 : BinOpMI8_RMW<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi8 : BinOpMI8_RMW<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL>;
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def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX>;
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@ -849,19 +909,78 @@ multiclass ArithBinOp_R<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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}
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} // Constraints = "$src1 = $dst"
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def #NAME#8mr : BinOpMR<BaseOpc, mnemonic, Xi8 , opnode>;
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def #NAME#16mr : BinOpMR<BaseOpc, mnemonic, Xi16, opnode>;
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def #NAME#32mr : BinOpMR<BaseOpc, mnemonic, Xi32, opnode>;
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def #NAME#64mr : BinOpMR<BaseOpc, mnemonic, Xi64, opnode>;
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def #NAME#8mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>;
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def #NAME#16mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>;
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def #NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>;
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def #NAME#64mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>;
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def #NAME#8mi : BinOpMI<mnemonic, Xi8 , opnode, MemMRM>;
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def #NAME#16mi : BinOpMI<mnemonic, Xi16, opnode, MemMRM>;
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def #NAME#32mi : BinOpMI<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi32 : BinOpMI<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#8mi : BinOpMI_RMW<mnemonic, Xi8 , opnode, MemMRM>;
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def #NAME#16mi : BinOpMI_RMW<mnemonic, Xi16, opnode, MemMRM>;
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def #NAME#32mi : BinOpMI_RMW<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi32 : BinOpMI_RMW<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#16mi8 : BinOpMI8<mnemonic, Xi16, opnode, MemMRM>;
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def #NAME#32mi8 : BinOpMI8<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi8 : BinOpMI8<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#16mi8 : BinOpMI8_RMW<mnemonic, Xi16, opnode, MemMRM>;
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def #NAME#32mi8 : BinOpMI8_RMW<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi8 : BinOpMI8_RMW<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL>;
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def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX>;
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def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX>;
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def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX>;
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}
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}
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/// ArithBinOp_F - This is an arithmetic binary operator where the pattern is
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/// defined with "(set EFLAGS, (...". It would be really nice to find a way
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/// to factor this with the other ArithBinOp_*.
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///
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multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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string mnemonic, Format RegMRM, Format MemMRM,
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SDNode opnode,
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bit CommutableRR, bit ConvertibleToThreeAddress> {
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let Defs = [EFLAGS] in {
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let isCommutable = CommutableRR,
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isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
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def #NAME#8rr : BinOpRR_F<BaseOpc, mnemonic, Xi8 , opnode>;
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def #NAME#16rr : BinOpRR_F<BaseOpc, mnemonic, Xi16, opnode>;
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def #NAME#32rr : BinOpRR_F<BaseOpc, mnemonic, Xi32, opnode>;
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def #NAME#64rr : BinOpRR_F<BaseOpc, mnemonic, Xi64, opnode>;
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} // isCommutable
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def #NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>;
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def #NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>;
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def #NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>;
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def #NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>;
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def #NAME#8rm : BinOpRM_F<BaseOpc2, mnemonic, Xi8 , opnode>;
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||||
def #NAME#16rm : BinOpRM_F<BaseOpc2, mnemonic, Xi16, opnode>;
|
||||
def #NAME#32rm : BinOpRM_F<BaseOpc2, mnemonic, Xi32, opnode>;
|
||||
def #NAME#64rm : BinOpRM_F<BaseOpc2, mnemonic, Xi64, opnode>;
|
||||
|
||||
let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
|
||||
def #NAME#8ri : BinOpRI_F<0x80, mnemonic, Xi8 , opnode, RegMRM>;
|
||||
def #NAME#16ri : BinOpRI_F<0x80, mnemonic, Xi16, opnode, RegMRM>;
|
||||
def #NAME#32ri : BinOpRI_F<0x80, mnemonic, Xi32, opnode, RegMRM>;
|
||||
def #NAME#64ri32: BinOpRI_F<0x80, mnemonic, Xi64, opnode, RegMRM>;
|
||||
|
||||
def #NAME#16ri8 : BinOpRI8_F<0x82, mnemonic, Xi16, opnode, RegMRM>;
|
||||
def #NAME#32ri8 : BinOpRI8_F<0x82, mnemonic, Xi32, opnode, RegMRM>;
|
||||
def #NAME#64ri8 : BinOpRI8_F<0x82, mnemonic, Xi64, opnode, RegMRM>;
|
||||
}
|
||||
|
||||
def #NAME#8mr : BinOpMR_F<BaseOpc, mnemonic, Xi8 , opnode>;
|
||||
def #NAME#16mr : BinOpMR_F<BaseOpc, mnemonic, Xi16, opnode>;
|
||||
def #NAME#32mr : BinOpMR_F<BaseOpc, mnemonic, Xi32, opnode>;
|
||||
def #NAME#64mr : BinOpMR_F<BaseOpc, mnemonic, Xi64, opnode>;
|
||||
|
||||
def #NAME#8mi : BinOpMI_F<mnemonic, Xi8 , opnode, MemMRM>;
|
||||
def #NAME#16mi : BinOpMI_F<mnemonic, Xi16, opnode, MemMRM>;
|
||||
def #NAME#32mi : BinOpMI_F<mnemonic, Xi32, opnode, MemMRM>;
|
||||
def #NAME#64mi32 : BinOpMI_F<mnemonic, Xi64, opnode, MemMRM>;
|
||||
|
||||
def #NAME#16mi8 : BinOpMI8_F<mnemonic, Xi16, opnode, MemMRM>;
|
||||
def #NAME#32mi8 : BinOpMI8_F<mnemonic, Xi32, opnode, MemMRM>;
|
||||
def #NAME#64mi8 : BinOpMI8_F<mnemonic, Xi64, opnode, MemMRM>;
|
||||
|
||||
def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL>;
|
||||
def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX>;
|
||||
@ -983,141 +1102,4 @@ def TEST64i32 : RIi32<0xa9, RawFrm, (outs), (ins i64i32imm:$src),
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Integer comparisons
|
||||
|
||||
let Defs = [EFLAGS] in {
|
||||
|
||||
def CMP8rr : I<0x38, MRMDestReg,
|
||||
(outs), (ins GR8 :$src1, GR8 :$src2),
|
||||
"cmp{b}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
|
||||
def CMP16rr : I<0x39, MRMDestReg,
|
||||
(outs), (ins GR16:$src1, GR16:$src2),
|
||||
"cmp{w}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
|
||||
def CMP32rr : I<0x39, MRMDestReg,
|
||||
(outs), (ins GR32:$src1, GR32:$src2),
|
||||
"cmp{l}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
|
||||
def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp GR64:$src1, GR64:$src2))]>;
|
||||
|
||||
def CMP8mr : I<0x38, MRMDestMem,
|
||||
(outs), (ins i8mem :$src1, GR8 :$src2),
|
||||
"cmp{b}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
|
||||
def CMP16mr : I<0x39, MRMDestMem,
|
||||
(outs), (ins i16mem:$src1, GR16:$src2),
|
||||
"cmp{w}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
|
||||
OpSize;
|
||||
def CMP32mr : I<0x39, MRMDestMem,
|
||||
(outs), (ins i32mem:$src1, GR32:$src2),
|
||||
"cmp{l}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
|
||||
def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp (loadi64 addr:$src1), GR64:$src2))]>;
|
||||
|
||||
def CMP8rm : I<0x3A, MRMSrcMem,
|
||||
(outs), (ins GR8 :$src1, i8mem :$src2),
|
||||
"cmp{b}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
|
||||
def CMP16rm : I<0x3B, MRMSrcMem,
|
||||
(outs), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmp{w}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
|
||||
OpSize;
|
||||
def CMP32rm : I<0x3B, MRMSrcMem,
|
||||
(outs), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmp{l}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
|
||||
def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp GR64:$src1, (loadi64 addr:$src2)))]>;
|
||||
|
||||
// These are alternate spellings for use by the disassembler, we mark them as
|
||||
// code gen only to ensure they aren't matched by the assembler.
|
||||
let isCodeGenOnly = 1 in {
|
||||
def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
|
||||
"cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
|
||||
def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
|
||||
"cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
|
||||
def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
|
||||
"cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
|
||||
def CMP64rr_alt : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
|
||||
}
|
||||
|
||||
def CMP8ri : Ii8<0x80, MRM7r,
|
||||
(outs), (ins GR8:$src1, i8imm:$src2),
|
||||
"cmp{b}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
|
||||
def CMP16ri : Ii16<0x81, MRM7r,
|
||||
(outs), (ins GR16:$src1, i16imm:$src2),
|
||||
"cmp{w}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
|
||||
def CMP32ri : Ii32<0x81, MRM7r,
|
||||
(outs), (ins GR32:$src1, i32imm:$src2),
|
||||
"cmp{l}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
|
||||
def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp GR64:$src1, i64immSExt32:$src2))]>;
|
||||
|
||||
def CMP8mi : Ii8 <0x80, MRM7m,
|
||||
(outs), (ins i8mem :$src1, i8imm :$src2),
|
||||
"cmp{b}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
|
||||
def CMP16mi : Ii16<0x81, MRM7m,
|
||||
(outs), (ins i16mem:$src1, i16imm:$src2),
|
||||
"cmp{w}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
|
||||
OpSize;
|
||||
def CMP32mi : Ii32<0x81, MRM7m,
|
||||
(outs), (ins i32mem:$src1, i32imm:$src2),
|
||||
"cmp{l}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
|
||||
def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
|
||||
(ins i64mem:$src1, i64i32imm:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp (loadi64 addr:$src1),
|
||||
i64immSExt32:$src2))]>;
|
||||
|
||||
def CMP16ri8 : Ii8<0x83, MRM7r,
|
||||
(outs), (ins GR16:$src1, i16i8imm:$src2),
|
||||
"cmp{w}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
|
||||
OpSize;
|
||||
def CMP32ri8 : Ii8<0x83, MRM7r,
|
||||
(outs), (ins GR32:$src1, i32i8imm:$src2),
|
||||
"cmp{l}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
|
||||
def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp GR64:$src1, i64immSExt8:$src2))]>;
|
||||
|
||||
def CMP16mi8 : Ii8<0x83, MRM7m,
|
||||
(outs), (ins i16mem:$src1, i16i8imm:$src2),
|
||||
"cmp{w}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp (loadi16 addr:$src1),
|
||||
i16immSExt8:$src2))]>, OpSize;
|
||||
def CMP32mi8 : Ii8<0x83, MRM7m,
|
||||
(outs), (ins i32mem:$src1, i32i8imm:$src2),
|
||||
"cmp{l}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp (loadi32 addr:$src1),
|
||||
i32immSExt8:$src2))]>;
|
||||
def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86cmp (loadi64 addr:$src1),
|
||||
i64immSExt8:$src2))]>;
|
||||
|
||||
def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
|
||||
"cmp{b}\t{$src, %al|%al, $src}", []>;
|
||||
def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
|
||||
"cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
|
||||
def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
|
||||
"cmp{l}\t{$src, %eax|%eax, $src}", []>;
|
||||
def CMP64i32 : RIi32<0x3D, RawFrm, (outs), (ins i64i32imm:$src),
|
||||
"cmp{q}\t{$src, %rax|%rax, $src}", []>;
|
||||
|
||||
} // Defs = [EFLAGS]
|
||||
defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
; RUN: llc < %s -march=x86 | grep cmp | count 1
|
||||
; RUN: llc < %s -march=x86 | grep test | count 1
|
||||
|
||||
define i32 @f1(i32 %X, i32* %y) {
|
||||
define i32 @f1(i32 %X, i32* %y) nounwind {
|
||||
%tmp = load i32* %y ; <i32> [#uses=1]
|
||||
%tmp.upgrd.1 = icmp eq i32 %tmp, 0 ; <i1> [#uses=1]
|
||||
br i1 %tmp.upgrd.1, label %ReturnBlock, label %cond_true
|
||||
@ -13,7 +13,7 @@ ReturnBlock: ; preds = %0
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
define i32 @f2(i32 %X, i32* %y) {
|
||||
define i32 @f2(i32 %X, i32* %y) nounwind {
|
||||
%tmp = load i32* %y ; <i32> [#uses=1]
|
||||
%tmp1 = shl i32 %tmp, 3 ; <i32> [#uses=1]
|
||||
%tmp1.upgrd.2 = icmp eq i32 %tmp1, 0 ; <i1> [#uses=1]
|
||||
|
||||
@ -20,8 +20,8 @@ bb: ; preds = %entry
|
||||
return: ; preds = %entry
|
||||
ret void
|
||||
; CHECK: memcmp2:
|
||||
; CHECK: movw (%rsi), %ax
|
||||
; CHECK: cmpw %ax, (%rdi)
|
||||
; CHECK: movw (%rdi), %ax
|
||||
; CHECK: cmpw (%rsi), %ax
|
||||
}
|
||||
|
||||
define void @memcmp2a(i8* %X, i32* nocapture %P) nounwind {
|
||||
@ -54,8 +54,8 @@ bb: ; preds = %entry
|
||||
return: ; preds = %entry
|
||||
ret void
|
||||
; CHECK: memcmp4:
|
||||
; CHECK: movl (%rsi), %eax
|
||||
; CHECK: cmpl %eax, (%rdi)
|
||||
; CHECK: movl (%rdi), %eax
|
||||
; CHECK: cmpl (%rsi), %eax
|
||||
}
|
||||
|
||||
define void @memcmp4a(i8* %X, i32* nocapture %P) nounwind {
|
||||
@ -87,8 +87,8 @@ bb: ; preds = %entry
|
||||
return: ; preds = %entry
|
||||
ret void
|
||||
; CHECK: memcmp8:
|
||||
; CHECK: movq (%rsi), %rax
|
||||
; CHECK: cmpq %rax, (%rdi)
|
||||
; CHECK: movq (%rdi), %rax
|
||||
; CHECK: cmpq (%rsi), %rax
|
||||
}
|
||||
|
||||
define void @memcmp8a(i8* %X, i32* nocapture %P) nounwind {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user