mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-02 16:56:50 +00:00
Use PC relative ldr to load from a constantpool in Thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33484 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
2b7218218f
commit
012f2d97b7
@ -245,6 +245,9 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &Fn,
|
||||
case ARMII::AddrModeT4:
|
||||
MaxOffs = 1 << (5+2);
|
||||
break;
|
||||
case ARMII::AddrModeTs:
|
||||
MaxOffs = 1 << (8+2);
|
||||
break;
|
||||
}
|
||||
|
||||
// Remember that this is a user of a CP entry.
|
||||
|
@ -380,6 +380,9 @@ ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDOperand Op, SDOperand N,
|
||||
SDOperand TmpBase, TmpOffImm;
|
||||
if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
|
||||
return false; // We want to select tLDRspi / tSTRspi instead.
|
||||
if (N.getOpcode() == ARMISD::Wrapper &&
|
||||
N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
|
||||
return false; // We want to select tLDRpci instead.
|
||||
}
|
||||
|
||||
if (N.getOpcode() != ISD::ADD) {
|
||||
@ -505,14 +508,20 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
|
||||
SDOperand CPIdx =
|
||||
CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
|
||||
TLI.getPointerTy());
|
||||
SDOperand Ops[] = {
|
||||
CPIdx,
|
||||
CurDAG->getRegister(0, MVT::i32),
|
||||
CurDAG->getTargetConstant(0, MVT::i32),
|
||||
CurDAG->getEntryNode()
|
||||
};
|
||||
SDNode *ResNode =
|
||||
CurDAG->getTargetNode(ARM::LDR, MVT::i32, MVT::Other, Ops, 4);
|
||||
|
||||
SDNode *ResNode;
|
||||
if (Subtarget->isThumb())
|
||||
ResNode = CurDAG->getTargetNode(ARM::tLDRpci, MVT::i32, MVT::Other,
|
||||
CPIdx, CurDAG->getEntryNode());
|
||||
else {
|
||||
SDOperand Ops[] = {
|
||||
CPIdx,
|
||||
CurDAG->getRegister(0, MVT::i32),
|
||||
CurDAG->getTargetConstant(0, MVT::i32),
|
||||
CurDAG->getEntryNode()
|
||||
};
|
||||
ResNode = CurDAG->getTargetNode(ARM::LDR, MVT::i32, MVT::Other, Ops, 4);
|
||||
}
|
||||
ReplaceUses(Op, SDOperand(ResNode, 0));
|
||||
return NULL;
|
||||
}
|
||||
|
@ -220,10 +220,14 @@ def tLDRSH : TI2<(ops GPR:$dst, t_addrmode_rr:$addr),
|
||||
"ldrsh $dst, $addr",
|
||||
[(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
|
||||
|
||||
// def tLDRpci
|
||||
def tLDRspi : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
|
||||
"ldr $dst, $addr",
|
||||
[(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
|
||||
|
||||
// Load tconstpool
|
||||
def tLDRpci : TIs<(ops GPR:$dst, i32imm:$addr),
|
||||
"ldr $dst, $addr",
|
||||
[(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
|
||||
} // isLoad
|
||||
|
||||
let isStore = 1 in {
|
||||
|
Loading…
Reference in New Issue
Block a user