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[AArch64] Fix PRR33100.

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This commit fixes a bug introduced in r301019 where optimizeLogicalImm
would replace a logical node's immediate operand that was CSE'd and
was also an operand of another node.

This commit fixes the bug by replacing the logical node instead of its
immediate operand.

rdar://problem/32295276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303607 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2017-05-23 06:08:37 +00:00
parent a1986434f8
commit 013125cca7
2 changed files with 29 additions and 7 deletions
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17
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -886,18 +886,21 @@ static bool optimizeLogicalImm(SDValue Op, unsigned Size, uint64_t Imm,
// Create the new constant immediate node.
EVT VT = Op.getValueType();
SDLoc DL(Op);
SDValue New;
// If the new constant immediate is all-zeros or all-ones, let the target
// independent DAG combine optimize this node.
if (NewImm == 0 || NewImm == OrigMask)
return TLO.CombineTo(Op.getOperand(1), TLO.DAG.getConstant(NewImm, DL, VT));
if (NewImm == 0 || NewImm == OrigMask) {
New = TLO.DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0),
TLO.DAG.getConstant(NewImm, DL, VT));
// Otherwise, create a machine node so that target independent DAG combine
// doesn't undo this optimization.
Enc = AArch64_AM::encodeLogicalImmediate(NewImm, Size);
SDValue EncConst = TLO.DAG.getTargetConstant(Enc, DL, VT);
SDValue New(
TLO.DAG.getMachineNode(NewOpc, DL, VT, Op.getOperand(0), EncConst), 0);
} else {
Enc = AArch64_AM::encodeLogicalImmediate(NewImm, Size);
SDValue EncConst = TLO.DAG.getTargetConstant(Enc, DL, VT);
New = SDValue(
TLO.DAG.getMachineNode(NewOpc, DL, VT, Op.getOperand(0), EncConst), 0);
}
return TLO.CombineTo(Op, New);
}

19
test/CodeGen/AArch64/optimize-imm.ll
View File

@ -62,3 +62,22 @@ entry:
%and = xor i32 %xor, 56
ret i32 %and
}
; Check that, when (and %t1, 129) is transformed to (and %t0, 0),
; (xor %arg, 129) doesn't get transformed to (xor %arg, 0).
;
; CHECK-LABEL: PR33100:
; CHECK: mov w[[R0:[0-9]+]], #129
; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, x[[R0]]
define i64 @PR33100(i64 %arg) {
entry:
%alloca0 = alloca i64
store i64 8, i64* %alloca0, align 4
%t0 = load i64, i64* %alloca0, align 4
%t1 = shl i64 %arg, %t0
%and0 = and i64 %t1, 129
%xor0 = xor i64 %arg, 129
%t2 = add i64 %and0, %xor0
ret i64 %t2
}