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R600: Fix nonsensical implementation of computeKnownBits for BFE

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This was resulting in invalid simplifications of sdiv

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219953 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-10-16 20:07:40 +00:00
parent 2f8f1d34e3
commit 0134a9bed3
2 changed files with 16 additions and 5 deletions
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6
lib/Target/R600/AMDGPUISelLowering.cpp
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@ -2377,11 +2377,7 @@ void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
unsigned BitWidth = 32;
uint32_t Width = CWidth->getZExtValue() & 0x1f;
// FIXME: This could do a lot more. If offset is 0, should be the same as
// sign_extend_inreg implementation, but that involves duplicating it.
if (Opc == AMDGPUISD::BFE_I32)
KnownOne = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
else
if (Opc == AMDGPUISD::BFE_U32)
KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
break;

15
test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll
View File

@ -424,3 +424,18 @@ define void @bfe_sext_in_reg_i24(i32 addrspace(1)* %out, i32 addrspace(1)* %in)
store i32 %ashr, i32 addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: @simplify_demanded_bfe_sdiv
; SI: BUFFER_LOAD_DWORD [[LOAD:v[0-9]+]]
; SI: V_BFE_I32 [[BFE:v[0-9]+]], [[LOAD]], 1, 16
; SI: V_LSHRREV_B32_e32 [[TMP0:v[0-9]+]], 31, [[BFE]]
; SI: V_ADD_I32_e32 [[TMP1:v[0-9]+]], [[TMP0]], [[BFE]]
; SI: V_ASHRREV_I32_e32 [[TMP2:v[0-9]+]], 1, [[TMP1]]
; SI: BUFFER_STORE_DWORD [[TMP2]]
define void @simplify_demanded_bfe_sdiv(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
%src = load i32 addrspace(1)* %in, align 4
%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %src, i32 1, i32 16) nounwind readnone
%div = sdiv i32 %bfe, 2
store i32 %div, i32 addrspace(1)* %out, align 4
ret void
}