mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-11 13:46:13 +00:00
fix some assumptions that pointers can only be 32-bits. With this, we can
now compile:
static unsigned long X;
void test1() {
X = 0;
}
into:
_test1:
lis r2, ha16(_X)
li r3, 0
stw r3, lo16(_X)(r2)
blr
Totally amazing :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28839 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
956f43c310
commit
059ca0f5b7
@ -128,7 +128,10 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
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setOperationAction(ISD::JumpTable, MVT::i32, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
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setOperationAction(ISD::JumpTable, MVT::i64, Custom);
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// RET must be custom lowered, to meet ABI requirements
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setOperationAction(ISD::RET , MVT::Other, Custom);
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@ -583,94 +586,94 @@ SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
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//===----------------------------------------------------------------------===//
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static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
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MVT::ValueType PtrVT = Op.getValueType();
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ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
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Constant *C = CP->get();
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SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32, CP->getAlignment());
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SDOperand Zero = DAG.getConstant(0, MVT::i32);
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SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
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SDOperand Zero = DAG.getConstant(0, PtrVT);
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const TargetMachine &TM = DAG.getTarget();
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SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
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SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
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// If this is a non-darwin platform, we don't support non-static relo models
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// yet.
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if (TM.getRelocationModel() == Reloc::Static ||
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!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
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// Generate non-pic code that has direct accesses to the constant pool.
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// The address of the global is just (hi(&g)+lo(&g)).
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SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
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SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
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return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
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return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
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}
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SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
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if (TM.getRelocationModel() == Reloc::PIC) {
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// With PIC, the first instruction is actually "GR+hi(&G)".
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Hi = DAG.getNode(ISD::ADD, MVT::i32,
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DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
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Hi = DAG.getNode(ISD::ADD, PtrVT,
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DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
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}
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SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
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Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
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Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
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return Lo;
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}
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static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
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MVT::ValueType PtrVT = Op.getValueType();
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JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
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SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
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SDOperand Zero = DAG.getConstant(0, MVT::i32);
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SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
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SDOperand Zero = DAG.getConstant(0, PtrVT);
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const TargetMachine &TM = DAG.getTarget();
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SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
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SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
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// If this is a non-darwin platform, we don't support non-static relo models
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// yet.
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if (TM.getRelocationModel() == Reloc::Static ||
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!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
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// Generate non-pic code that has direct accesses to the constant pool.
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// The address of the global is just (hi(&g)+lo(&g)).
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SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, JTI, Zero);
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SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, JTI, Zero);
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return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
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return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
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}
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SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, JTI, Zero);
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if (TM.getRelocationModel() == Reloc::PIC) {
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// With PIC, the first instruction is actually "GR+hi(&G)".
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Hi = DAG.getNode(ISD::ADD, MVT::i32,
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Hi = DAG.getNode(ISD::ADD, PtrVT,
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DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
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}
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SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, JTI, Zero);
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Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
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Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
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return Lo;
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}
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static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
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MVT::ValueType PtrVT = Op.getValueType();
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GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
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GlobalValue *GV = GSDN->getGlobal();
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SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset());
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SDOperand Zero = DAG.getConstant(0, MVT::i32);
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SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
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SDOperand Zero = DAG.getConstant(0, PtrVT);
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const TargetMachine &TM = DAG.getTarget();
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SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
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SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
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// If this is a non-darwin platform, we don't support non-static relo models
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// yet.
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if (TM.getRelocationModel() == Reloc::Static ||
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!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
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// Generate non-pic code that has direct accesses to globals.
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// The address of the global is just (hi(&g)+lo(&g)).
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SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
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SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
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return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
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return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
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}
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SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
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if (TM.getRelocationModel() == Reloc::PIC) {
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// With PIC, the first instruction is actually "GR+hi(&G)".
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Hi = DAG.getNode(ISD::ADD, MVT::i32,
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DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
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Hi = DAG.getNode(ISD::ADD, PtrVT,
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DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
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}
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SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
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Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
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Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
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if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() &&
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(!GV->isExternal() || GV->hasNotBeenReadFromBytecode()))
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@ -678,7 +681,7 @@ static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
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// If the global is weak or external, we have to go through the lazy
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// resolution stub.
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return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
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return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
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}
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static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
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@ -105,6 +105,13 @@ def RLDICR : MDForm_1<30, 1,
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let isLoad = 1, PPC970_Unit = 2 in {
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def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
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"lwa $rT, $DS($rA)", LdStLWA,
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[]>, isPPC64, PPC970_DGroup_Cracked;
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def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
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"ld $rT, $DS($rA)", LdStLD,
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[]>, isPPC64;
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def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
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"lwax $rD, $src", LdStLHA,
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[(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64,
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@ -113,23 +120,18 @@ def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
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"ldx $rD, $src", LdStLD,
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[(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
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}
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// DS-Form instructions. Load/Store instructions available in PPC-64
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//
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let isLoad = 1, PPC970_Unit = 2 in {
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def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
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"lwa $rT, $DS($rA)", LdStLWA,
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[]>, isPPC64, PPC970_DGroup_Cracked;
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def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
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"ld $rT, $DS($rA)", LdStLD,
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[]>, isPPC64;
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}
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let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
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def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
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"std $rT, $DS($rA)", LdStSTD,
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[]>, isPPC64;
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def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stdx $rS, $rA, $rB", LdStSTD,
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[]>, isPPC64, PPC970_DGroup_Cracked;
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def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stdux $rS, $rA, $rB", LdStSTD,
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[]>, isPPC64;
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// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
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def STD_32 : DSForm_2<62, 0, (ops GPRC:$rT, memrix:$dst),
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"std $rT, $dst", LdStSTD,
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@ -138,13 +140,6 @@ def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst),
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"stdx $rT, $dst", LdStSTD,
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[(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
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PPC970_DGroup_Cracked;
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def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stdx $rS, $rA, $rB", LdStSTD,
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[]>, isPPC64, PPC970_DGroup_Cracked;
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def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stdux $rS, $rA, $rB", LdStSTD,
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[]>, isPPC64;
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}
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@ -183,13 +183,13 @@ def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
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def target : Operand<OtherVT> {
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let PrintMethod = "printBranchOperand";
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}
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def calltarget : Operand<i32> {
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def calltarget : Operand<iPTR> {
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let PrintMethod = "printCallOperand";
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}
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def aaddr : Operand<i32> {
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def aaddr : Operand<iPTR> {
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let PrintMethod = "printAbsAddrOperand";
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}
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def piclabel: Operand<i32> {
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def piclabel: Operand<iPTR> {
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let PrintMethod = "printPICLabel";
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}
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def symbolHi: Operand<i32> {
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@ -202,27 +202,27 @@ def crbitm: Operand<i8> {
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let PrintMethod = "printcrbitm";
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}
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// Address operands
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def memri : Operand<i32> {
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def memri : Operand<iPTR> {
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let PrintMethod = "printMemRegImm";
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let NumMIOperands = 2;
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let MIOperandInfo = (ops i32imm, GPRC);
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}
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def memrr : Operand<i32> {
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def memrr : Operand<iPTR> {
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let PrintMethod = "printMemRegReg";
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let NumMIOperands = 2;
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let MIOperandInfo = (ops GPRC, GPRC);
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}
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def memrix : Operand<i32> { // memri where the imm is shifted 2 bits.
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def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
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let PrintMethod = "printMemRegImmShifted";
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let NumMIOperands = 2;
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let MIOperandInfo = (ops i32imm, GPRC);
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}
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// Define PowerPC specific addressing mode.
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def iaddr : ComplexPattern<i32, 2, "SelectAddrImm", []>;
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def xaddr : ComplexPattern<i32, 2, "SelectAddrIdx", []>;
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def xoaddr : ComplexPattern<i32, 2, "SelectAddrIdxOnly",[]>;
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def ixaddr : ComplexPattern<i32, 2, "SelectAddrImmShift", []>; // "std"
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def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", []>;
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def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", []>;
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def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[]>;
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def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", []>; // "std"
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//===----------------------------------------------------------------------===//
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// PowerPC Instruction Predicate Definitions.
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@ -957,6 +957,5 @@ def : Pat<(f64 (extload iaddr:$src, f32)),
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def : Pat<(f64 (extload xaddr:$src, f32)),
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(FMRSD (LFSX xaddr:$src))>;
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include "PPCInstrAltivec.td"
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include "PPCInstr64Bit.td"
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