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[AArch64][LoadStoreOptimizer] Generate LDP + SXTW instead of LD[U]R + LD[U]RSW.
Teach the load store optimizer how to sign extend a result of a load pair when it helps creating more pairs. The rational is that loads are more expensive than sign extensions, so if we gather some in one instruction this is better! <rdar://problem/20072968> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231527 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet
parent
5bac8f9b95
commit
05a3f9120a
@ -63,16 +63,24 @@ struct AArch64LoadStoreOpt : public MachineFunctionPass {
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// If a matching instruction is found, MergeForward is set to true if the
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// merge is to remove the first instruction and replace the second with
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// a pair-wise insn, and false if the reverse is true.
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// \p SExtIdx[out] gives the index of the result of the load pair that
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// must be extended. The value of SExtIdx assumes that the paired load
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// produces the value in this order: (I, returned iterator), i.e.,
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// -1 means no value has to be extended, 0 means I, and 1 means the
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// returned iterator.
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MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator I,
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bool &MergeForward,
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bool &MergeForward, int &SExtIdx,
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unsigned Limit);
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// Merge the two instructions indicated into a single pair-wise instruction.
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// If MergeForward is true, erase the first instruction and fold its
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// operation into the second. If false, the reverse. Return the instruction
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// following the first instruction (which may change during processing).
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// \p SExtIdx index of the result that must be extended for a paired load.
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// -1 means none, 0 means I, and 1 means Paired.
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MachineBasicBlock::iterator
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mergePairedInsns(MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Paired, bool MergeForward);
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MachineBasicBlock::iterator Paired, bool MergeForward,
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int SExtIdx);
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// Scan the instruction list to find a base register update that can
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// be combined with the current instruction (a load or store) using
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@ -181,6 +189,43 @@ int AArch64LoadStoreOpt::getMemSize(MachineInstr *MemMI) {
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}
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}
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static unsigned getMatchingNonSExtOpcode(unsigned Opc,
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bool *IsValidLdStrOpc = nullptr) {
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if (IsValidLdStrOpc)
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*IsValidLdStrOpc = true;
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switch (Opc) {
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default:
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if (IsValidLdStrOpc)
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*IsValidLdStrOpc = false;
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return UINT_MAX;
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case AArch64::STRDui:
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case AArch64::STURDi:
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case AArch64::STRQui:
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case AArch64::STURQi:
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case AArch64::STRWui:
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case AArch64::STURWi:
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case AArch64::STRXui:
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case AArch64::STURXi:
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case AArch64::LDRDui:
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case AArch64::LDURDi:
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case AArch64::LDRQui:
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case AArch64::LDURQi:
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case AArch64::LDRWui:
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case AArch64::LDURWi:
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case AArch64::LDRXui:
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case AArch64::LDURXi:
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case AArch64::STRSui:
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case AArch64::STURSi:
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case AArch64::LDRSui:
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case AArch64::LDURSi:
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return Opc;
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case AArch64::LDRSWui:
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return AArch64::LDRWui;
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case AArch64::LDURSWi:
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return AArch64::LDURWi;
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}
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}
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static unsigned getMatchingPairOpcode(unsigned Opc) {
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switch (Opc) {
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default:
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@ -282,7 +327,7 @@ static unsigned getPostIndexedOpcode(unsigned Opc) {
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MachineBasicBlock::iterator
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AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Paired,
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bool MergeForward) {
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bool MergeForward, int SExtIdx) {
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MachineBasicBlock::iterator NextI = I;
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++NextI;
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// If NextI is the second of the two instructions to be merged, we need
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@ -292,11 +337,13 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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if (NextI == Paired)
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++NextI;
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bool IsUnscaled = isUnscaledLdst(I->getOpcode());
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unsigned Opc =
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SExtIdx == -1 ? I->getOpcode() : getMatchingNonSExtOpcode(I->getOpcode());
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bool IsUnscaled = isUnscaledLdst(Opc);
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int OffsetStride =
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IsUnscaled && EnableAArch64UnscaledMemOp ? getMemSize(I) : 1;
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unsigned NewOpc = getMatchingPairOpcode(I->getOpcode());
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unsigned NewOpc = getMatchingPairOpcode(Opc);
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// Insert our new paired instruction after whichever of the paired
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// instructions MergeForward indicates.
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MachineBasicBlock::iterator InsertionPoint = MergeForward ? Paired : I;
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@ -311,6 +358,11 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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Paired->getOperand(2).getImm() + OffsetStride) {
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RtMI = Paired;
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Rt2MI = I;
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// Here we swapped the assumption made for SExtIdx.
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// I.e., we turn ldp I, Paired into ldp Paired, I.
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// Update the index accordingly.
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if (SExtIdx != -1)
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SExtIdx = (SExtIdx + 1) % 2;
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} else {
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RtMI = I;
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Rt2MI = Paired;
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@ -337,8 +389,47 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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DEBUG(dbgs() << " ");
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DEBUG(Paired->print(dbgs()));
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DEBUG(dbgs() << " with instruction:\n ");
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DEBUG(((MachineInstr *)MIB)->print(dbgs()));
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DEBUG(dbgs() << "\n");
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if (SExtIdx != -1) {
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// Generate the sign extension for the proper result of the ldp.
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// I.e., with X1, that would be:
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// %W1<def> = KILL %W1, %X1<imp-def>
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// %X1<def> = SBFMXri %X1<kill>, 0, 31
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MachineOperand &DstMO = MIB->getOperand(SExtIdx);
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// Right now, DstMO has the extended register, since it comes from an
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// extended opcode.
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unsigned DstRegX = DstMO.getReg();
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// Get the W variant of that register.
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unsigned DstRegW = TRI->getSubReg(DstRegX, AArch64::sub_32);
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// Update the result of LDP to use the W instead of the X variant.
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DstMO.setReg(DstRegW);
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DEBUG(((MachineInstr *)MIB)->print(dbgs()));
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DEBUG(dbgs() << "\n");
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// Make the machine verifier happy by providing a definition for
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// the X register.
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// Insert this definition right after the generated LDP, i.e., before
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// InsertionPoint.
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MachineInstrBuilder MIBKill =
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BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
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TII->get(TargetOpcode::KILL), DstRegW)
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.addReg(DstRegW)
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.addReg(DstRegX, RegState::Define);
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MIBKill->getOperand(2).setImplicit();
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// Create the sign extension.
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MachineInstrBuilder MIBSXTW =
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BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
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TII->get(AArch64::SBFMXri), DstRegX)
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.addReg(DstRegX)
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.addImm(0)
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.addImm(31);
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(void)MIBSXTW;
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DEBUG(dbgs() << " Extend operand:\n ");
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DEBUG(((MachineInstr *)MIBSXTW)->print(dbgs()));
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DEBUG(dbgs() << "\n");
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} else {
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DEBUG(((MachineInstr *)MIB)->print(dbgs()));
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DEBUG(dbgs() << "\n");
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}
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// Erase the old instructions.
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I->eraseFromParent();
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@ -396,7 +487,8 @@ static int alignTo(int Num, int PowOf2) {
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/// be combined with the current instruction into a load/store pair.
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MachineBasicBlock::iterator
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AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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bool &MergeForward, unsigned Limit) {
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bool &MergeForward, int &SExtIdx,
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unsigned Limit) {
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MachineBasicBlock::iterator E = I->getParent()->end();
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MachineBasicBlock::iterator MBBI = I;
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MachineInstr *FirstMI = I;
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@ -436,7 +528,19 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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// Now that we know this is a real instruction, count it.
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++Count;
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if (Opc == MI->getOpcode() && MI->getOperand(2).isImm()) {
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bool CanMergeOpc = Opc == MI->getOpcode();
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SExtIdx = -1;
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if (!CanMergeOpc) {
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bool IsValidLdStrOpc;
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unsigned NonSExtOpc = getMatchingNonSExtOpcode(Opc, &IsValidLdStrOpc);
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if (!IsValidLdStrOpc)
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continue;
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// Opc will be the first instruction in the pair.
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SExtIdx = NonSExtOpc == (unsigned)Opc ? 1 : 0;
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CanMergeOpc = NonSExtOpc == getMatchingNonSExtOpcode(MI->getOpcode());
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}
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if (CanMergeOpc && MI->getOperand(2).isImm()) {
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// If we've found another instruction with the same opcode, check to see
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// if the base and offset are compatible with our starting instruction.
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// These instructions all have scaled immediate operands, so we just
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@ -823,13 +927,14 @@ bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB) {
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}
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// Look ahead up to ScanLimit instructions for a pairable instruction.
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bool MergeForward = false;
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int SExtIdx = -1;
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MachineBasicBlock::iterator Paired =
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findMatchingInsn(MBBI, MergeForward, ScanLimit);
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findMatchingInsn(MBBI, MergeForward, SExtIdx, ScanLimit);
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if (Paired != E) {
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// Merge the loads into a pair. Keeping the iterator straight is a
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// pain, so we let the merge routine tell us what the next instruction
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// is after it's done mucking about.
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MBBI = mergePairedInsns(MBBI, Paired, MergeForward);
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MBBI = mergePairedInsns(MBBI, Paired, MergeForward, SExtIdx);
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Modified = true;
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++NumPairCreated;
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@ -24,6 +24,33 @@ define i64 @ldp_sext_int(i32* %p) nounwind {
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ret i64 %add
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}
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; CHECK-LABEL: ldp_half_sext_res0_int:
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; CHECK: ldp w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0]
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; CHECK: sxtw x[[DST1]], w[[DST1]]
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define i64 @ldp_half_sext_res0_int(i32* %p) nounwind {
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%tmp = load i32, i32* %p, align 4
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%add.ptr = getelementptr inbounds i32, i32* %p, i64 1
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%tmp1 = load i32, i32* %add.ptr, align 4
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%sexttmp = sext i32 %tmp to i64
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%sexttmp1 = zext i32 %tmp1 to i64
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%add = add nsw i64 %sexttmp1, %sexttmp
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ret i64 %add
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}
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; CHECK-LABEL: ldp_half_sext_res1_int:
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; CHECK: ldp w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0]
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; CHECK: sxtw x[[DST2]], w[[DST2]]
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define i64 @ldp_half_sext_res1_int(i32* %p) nounwind {
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%tmp = load i32, i32* %p, align 4
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%add.ptr = getelementptr inbounds i32, i32* %p, i64 1
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%tmp1 = load i32, i32* %add.ptr, align 4
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%sexttmp = zext i32 %tmp to i64
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%sexttmp1 = sext i32 %tmp1 to i64
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%add = add nsw i64 %sexttmp1, %sexttmp
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ret i64 %add
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}
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; CHECK: ldp_long
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; CHECK: ldp
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define i64 @ldp_long(i64* %p) nounwind {
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@ -83,6 +110,39 @@ define i64 @ldur_sext_int(i32* %a) nounwind {
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ret i64 %tmp3
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}
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define i64 @ldur_half_sext_int_res0(i32* %a) nounwind {
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; LDUR_CHK: ldur_half_sext_int_res0
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; LDUR_CHK: ldp w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0, #-8]
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; LDUR_CHK: sxtw x[[DST1]], w[[DST1]]
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; LDUR_CHK-NEXT: add x{{[0-9]+}}, x[[DST2]], x[[DST1]]
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; LDUR_CHK-NEXT: ret
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%p1 = getelementptr inbounds i32, i32* %a, i32 -1
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%tmp1 = load i32, i32* %p1, align 2
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%p2 = getelementptr inbounds i32, i32* %a, i32 -2
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%tmp2 = load i32, i32* %p2, align 2
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%sexttmp1 = zext i32 %tmp1 to i64
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%sexttmp2 = sext i32 %tmp2 to i64
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%tmp3 = add i64 %sexttmp1, %sexttmp2
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ret i64 %tmp3
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}
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define i64 @ldur_half_sext_int_res1(i32* %a) nounwind {
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; LDUR_CHK: ldur_half_sext_int_res1
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; LDUR_CHK: ldp w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0, #-8]
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; LDUR_CHK: sxtw x[[DST2]], w[[DST2]]
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; LDUR_CHK-NEXT: add x{{[0-9]+}}, x[[DST2]], x[[DST1]]
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; LDUR_CHK-NEXT: ret
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%p1 = getelementptr inbounds i32, i32* %a, i32 -1
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%tmp1 = load i32, i32* %p1, align 2
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%p2 = getelementptr inbounds i32, i32* %a, i32 -2
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%tmp2 = load i32, i32* %p2, align 2
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%sexttmp1 = sext i32 %tmp1 to i64
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%sexttmp2 = zext i32 %tmp2 to i64
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%tmp3 = add i64 %sexttmp1, %sexttmp2
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ret i64 %tmp3
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}
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define i64 @ldur_long(i64* %a) nounwind ssp {
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; LDUR_CHK: ldur_long
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; LDUR_CHK: ldp [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-16]
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@ -153,6 +213,40 @@ define i64 @pairUpBarelyInSext(i32* %a) nounwind ssp {
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ret i64 %tmp3
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}
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define i64 @pairUpBarelyInHalfSextRes0(i32* %a) nounwind ssp {
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; LDUR_CHK: pairUpBarelyInHalfSextRes0
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; LDUR_CHK-NOT: ldur
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; LDUR_CHK: ldp w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0, #-256]
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; LDUR_CHK: sxtw x[[DST1]], w[[DST1]]
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; LDUR_CHK-NEXT: add x{{[0-9]+}}, x[[DST2]], x[[DST1]]
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; LDUR_CHK-NEXT: ret
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%p1 = getelementptr inbounds i32, i32* %a, i64 -63
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%tmp1 = load i32, i32* %p1, align 2
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%p2 = getelementptr inbounds i32, i32* %a, i64 -64
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%tmp2 = load i32, i32* %p2, align 2
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%sexttmp1 = zext i32 %tmp1 to i64
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%sexttmp2 = sext i32 %tmp2 to i64
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%tmp3 = add i64 %sexttmp1, %sexttmp2
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ret i64 %tmp3
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}
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define i64 @pairUpBarelyInHalfSextRes1(i32* %a) nounwind ssp {
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; LDUR_CHK: pairUpBarelyInHalfSextRes1
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; LDUR_CHK-NOT: ldur
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; LDUR_CHK: ldp w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0, #-256]
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; LDUR_CHK: sxtw x[[DST2]], w[[DST2]]
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; LDUR_CHK-NEXT: add x{{[0-9]+}}, x[[DST2]], x[[DST1]]
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; LDUR_CHK-NEXT: ret
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%p1 = getelementptr inbounds i32, i32* %a, i64 -63
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%tmp1 = load i32, i32* %p1, align 2
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%p2 = getelementptr inbounds i32, i32* %a, i64 -64
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%tmp2 = load i32, i32* %p2, align 2
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%sexttmp1 = sext i32 %tmp1 to i64
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%sexttmp2 = zext i32 %tmp2 to i64
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%tmp3 = add i64 %sexttmp1, %sexttmp2
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ret i64 %tmp3
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}
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define i64 @pairUpBarelyOut(i64* %a) nounwind ssp {
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; LDUR_CHK: pairUpBarelyOut
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; LDUR_CHK-NOT: ldp
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