RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2025-04-02 08:11:54 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Delete trailing whitespace; NFC

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256906 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Junmo Park 2016-01-06 03:41:30 +00:00
parent bf6a00569e
commit 05e99849bf
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
View File

@ -158,7 +158,7 @@ INITIALIZE_PASS_END(AArch64A57FPLoadBalancing, DEBUG_TYPE,
"AArch64 A57 FP Load-Balancing", false, false)
namespace {
/// A Chain is a sequence of instructions that are linked together by
/// A Chain is a sequence of instructions that are linked together by
/// an accumulation operand. For example:
///
/// fmul d0<def>, ?
@ -285,7 +285,7 @@ public:
std::string str() const {
std::string S;
raw_string_ostream OS(S);
OS << "{";
StartInst->print(OS, /* SkipOpers= */true);
OS << " -> ";
@ -427,7 +427,7 @@ Chain *AArch64A57FPLoadBalancing::getAndEraseNext(Color PreferredColor,
return Ch;
}
}
// Bailout case - just return the first item.
Chain *Ch = L.front();
L.erase(L.begin());
@ -495,7 +495,7 @@ int AArch64A57FPLoadBalancing::scavengeRegister(Chain *G, Color C,
RS.enterBasicBlock(&MBB);
RS.forward(MachineBasicBlock::iterator(G->getStart()));
// Can we find an appropriate register that is available throughout the life
// Can we find an appropriate register that is available throughout the life
// of the chain?
unsigned RegClassID = G->getStart()->getDesc().OpInfo[0].RegClass;
BitVector AvailableRegs = RS.getRegsAvailable(TRI->getRegClass(RegClassID));