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[mips] Macro expansion for ld, sd for O32
ld and sd when assembled for the O32 ABI expand to a pair of 32 bit word loads or stores using the specified source or destination register and the next register. This patch does not add support for the cases where the offset is greater than a 16 bit signed immediate as that would lead to a wrong/misleading error message as the assembler would report "instruction requires a CPU feature not currently enabled" for ld & sd for MIPS64 when their offset is not a signed 16 bit number. This fixes PR/29159. Thanks to Sean Bruno for reporting this issue! Reviewers: vkalintiris, seanbruno, zoran.jovanovic Differential Review: https://reviews.llvm.org/D24556 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284481 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Dardis
parent
d5f902eb11
commit
05fe9f3914
@ -249,6 +249,9 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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bool expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI, bool IsLoad);
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bool reportParseError(Twine ErrorMsg);
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bool reportParseError(SMLoc Loc, Twine ErrorMsg);
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@ -2213,6 +2216,12 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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return expandDRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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case Mips::ABSMacro:
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return expandAbs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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case Mips::LDMacro:
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case Mips::SDMacro:
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return expandLoadStoreDMacro(Inst, IDLoc, Out, STI,
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Inst.getOpcode() == Mips::LDMacro)
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? MER_Fail
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: MER_Success;
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}
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}
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@ -3819,6 +3828,92 @@ bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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return false;
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}
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static unsigned nextReg(unsigned Reg) {
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switch (Reg) {
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case Mips::ZERO: return Mips::AT;
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case Mips::AT: return Mips::V0;
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case Mips::V0: return Mips::V1;
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case Mips::V1: return Mips::A0;
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case Mips::A0: return Mips::A1;
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case Mips::A1: return Mips::A2;
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case Mips::A2: return Mips::A3;
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case Mips::A3: return Mips::T0;
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case Mips::T0: return Mips::T1;
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case Mips::T1: return Mips::T2;
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case Mips::T2: return Mips::T3;
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case Mips::T3: return Mips::T4;
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case Mips::T4: return Mips::T5;
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case Mips::T5: return Mips::T6;
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case Mips::T6: return Mips::T7;
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case Mips::T7: return Mips::S0;
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case Mips::S0: return Mips::S1;
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case Mips::S1: return Mips::S2;
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case Mips::S2: return Mips::S3;
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case Mips::S3: return Mips::S4;
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case Mips::S4: return Mips::S5;
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case Mips::S5: return Mips::S6;
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case Mips::S6: return Mips::S7;
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case Mips::S7: return Mips::T8;
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case Mips::T8: return Mips::T9;
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case Mips::T9: return Mips::K0;
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case Mips::K0: return Mips::K1;
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case Mips::K1: return Mips::GP;
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case Mips::GP: return Mips::SP;
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case Mips::SP: return Mips::FP;
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case Mips::FP: return Mips::RA;
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case Mips::RA: return Mips::ZERO;
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default: return 0;
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}
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}
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// Expand 'ld $<reg> offset($reg2)' to 'lw $<reg>, offset($reg2);
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// lw $<reg+1>>, offset+4($reg2)'
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// or expand 'sd $<reg> offset($reg2)' to 'sw $<reg>, offset($reg2);
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// sw $<reg+1>>, offset+4($reg2)'
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// for O32.
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bool MipsAsmParser::expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc,
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MCStreamer &Out,
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const MCSubtargetInfo *STI,
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bool IsLoad) {
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if (!isABI_O32())
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return true;
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warnIfNoMacro(IDLoc);
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MipsTargetStreamer &TOut = getTargetStreamer();
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unsigned Opcode = IsLoad ? Mips::LW : Mips::SW;
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unsigned FirstReg = Inst.getOperand(0).getReg();
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unsigned SecondReg = nextReg(FirstReg);
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unsigned BaseReg = Inst.getOperand(1).getReg();
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if (!SecondReg)
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return true;
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warnIfRegIndexIsAT(FirstReg, IDLoc);
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assert(Inst.getOperand(2).isImm() &&
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"Offset for load macro is not immediate!");
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MCOperand &FirstOffset = Inst.getOperand(2);
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signed NextOffset = FirstOffset.getImm() + 4;
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MCOperand SecondOffset = MCOperand::createImm(NextOffset);
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if (!isInt<16>(FirstOffset.getImm()) || !isInt<16>(NextOffset))
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return true;
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// For loads, clobber the base register with the second load instead of the
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// first if the BaseReg == FirstReg.
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if (FirstReg != BaseReg || !IsLoad) {
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TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);
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TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);
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} else {
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TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);
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TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);
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}
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return false;
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}
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unsigned
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MipsAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst,
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const OperandVector &Operands) {
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@ -157,6 +157,8 @@ def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
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AssemblerPredicate<"FeatureMips3_32r2">;
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def HasMips3 : Predicate<"Subtarget->hasMips3()">,
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AssemblerPredicate<"FeatureMips3">;
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def NotMips3 : Predicate<"!Subtarget->hasMips3()">,
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AssemblerPredicate<"!FeatureMips3">;
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def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
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AssemblerPredicate<"FeatureMips4_32">;
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def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">,
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@ -242,6 +244,9 @@ class PTR_64 { list<Predicate> PTRPredicates = [IsPTR64bit]; }
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// subtractive predicate will hopefully keep us under the 32 predicate
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// limit long enough to develop an alternative way to handle P1||P2
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// predicates.
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class ISA_MIPS1_NOT_MIPS3 {
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list<Predicate> InsnPredicates = [NotMips3];
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}
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class ISA_MIPS1_NOT_4_32 {
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list<Predicate> InsnPredicates = [NotMips4_32];
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}
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@ -2541,6 +2546,12 @@ def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
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def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
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"ulw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
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def LDMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
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(ins mem_simm16:$addr), "ld $rt, $addr">,
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ISA_MIPS1_NOT_MIPS3;
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def SDMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
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(ins mem_simm16:$addr), "sd $rt, $addr">,
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ISA_MIPS1_NOT_MIPS3;
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//===----------------------------------------------------------------------===//
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// Arbitrary patterns that map to one or more instructions
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//===----------------------------------------------------------------------===//
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24
test/MC/Mips/macro-ld-sd.s
Normal file
24
test/MC/Mips/macro-ld-sd.s
Normal file
@ -0,0 +1,24 @@
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# RUN: llvm-mc -triple mips-mti-linux-gnu -show-encoding %s | FileCheck \
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# RUN: --check-prefixes=ALL,32 %s
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# RUN: llvm-mc -triple mips64-mti-linux-gnu -show-encoding %s -target-abi n64 \
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# RUN: | FileCheck --check-prefixes=ALL,64 %s
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# RUN: llvm-mc -triple mips64-mti-linux-gnu -show-encoding %s -target-abi n32 \
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# RUN: | FileCheck --check-prefixes=ALL,64 %s
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# ALL: .text
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ld $8, 0($5)
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# 32: lw $8, 0($5) # encoding: [0x8c,0xa8,0x00,0x00]
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# 32: lw $9, 4($5) # encoding: [0x8c,0xa9,0x00,0x04]
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# 64: ld $8, 0($5) # encoding: [0xdc,0xa8,0x00,0x00]
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sd $8, 0($5)
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# 32: sw $8, 0($5) # encoding: [0xac,0xa8,0x00,0x00]
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# 32: sw $9, 4($5) # encoding: [0xac,0xa9,0x00,0x04]
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# 64: sd $8, 0($5) # encoding: [0xfc,0xa8,0x00,0x00]
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ld $8, 0($8)
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# 32: lw $9, 4($8) # encoding: [0x8d,0x09,0x00,0x04]
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# 32: lw $8, 0($8) # encoding: [0x8d,0x08,0x00,0x00]
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# 64: ld $8, 0($8) # encoding: [0xdd,0x08,0x00,0x00]
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sd $8, 0($8)
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# 32: sw $8, 0($8) # encoding: [0xad,0x08,0x00,0x00]
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# 32: sw $9, 4($8) # encoding: [0xad,0x09,0x00,0x04]
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# 64: sd $8, 0($8) # encoding: [0xfd,0x08,0x00,0x00]
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@ -54,14 +54,12 @@
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floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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floor.w.d $f14,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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floor.w.s $f8,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
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lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
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lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset
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round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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sd $12,5835($10) # CHECK: :[[@LINE]]:23: error: expected memory with 16-bit signed offset
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sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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@ -69,14 +69,12 @@
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movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
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lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
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lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset
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round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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sd $12,5835($10) # CHECK: :[[@LINE]]:23: error: expected memory with 16-bit signed offset
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sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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@ -50,11 +50,9 @@
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eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
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lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
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lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:24: error: expected memory with 12-bit signed offset
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round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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sd $t0,5835($a6) # CHECK: :[[@LINE]]:24: error: expected memory with 16-bit signed offset
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trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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@ -66,10 +66,8 @@
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movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
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round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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sd $12,5835($10) # CHECK: :[[@LINE]]:23: error: expected memory with 16-bit signed offset
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sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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