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AMDGPU: Fix inconsistent lowering of select of vectors
f32 vectors would use a sequence of BFI instructions instead of unrolled cmp + select. This was better in the case of a VALU select with SGPR inputs, but we don't have a way of dealing with that in the DAG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270731 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
cab076f44c
commit
068cdecac2
@ -424,13 +424,21 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
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setOperationAction(ISD::FSIN, VT, Expand);
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setOperationAction(ISD::FSUB, VT, Expand);
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setOperationAction(ISD::FNEG, VT, Expand);
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setOperationAction(ISD::SELECT, VT, Expand);
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setOperationAction(ISD::VSELECT, VT, Expand);
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setOperationAction(ISD::SELECT_CC, VT, Expand);
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setOperationAction(ISD::FCOPYSIGN, VT, Expand);
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
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}
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// This causes using an unrolled select operation rather than expansion with
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// bit operations. This is in general better, but the alternative using BFI
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// instructions may be better if the select sources are SGPRs.
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setOperationAction(ISD::SELECT, MVT::v2f32, Promote);
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AddPromotedToType(ISD::SELECT, MVT::v2f32, MVT::v2i32);
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setOperationAction(ISD::SELECT, MVT::v4f32, Promote);
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AddPromotedToType(ISD::SELECT, MVT::v4f32, MVT::v4i32);
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setBooleanContents(ZeroOrNegativeOneBooleanContent);
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setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
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@ -1,4 +1,4 @@
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; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -verify-machineinstrs -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; Test expansion of scalar selects on vectors.
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@ -29,30 +29,50 @@ define void @select_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %a, <4 x i16>
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ret void
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}
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; FUNC-LABEL: {{^}}select_v2i32:
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; FIXME: Expansion with bitwise operations may be better if doing a
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; vector select with SGPR inputs.
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; FUNC-LABEL: {{^}}s_select_v2i32:
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; SI: v_cndmask_b32_e32
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; SI: v_cndmask_b32_e32
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; SI: buffer_store_dwordx2
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define void @select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b, i32 %c) nounwind {
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define void @s_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b, i32 %c) nounwind {
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%cmp = icmp eq i32 %c, 0
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%select = select i1 %cmp, <2 x i32> %a, <2 x i32> %b
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store <2 x i32> %select, <2 x i32> addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}select_v4i32:
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; FUNC-LABEL: {{^}}s_select_v4i32:
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; SI: v_cndmask_b32_e32
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; SI: v_cndmask_b32_e32
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; SI: v_cndmask_b32_e32
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; SI: v_cndmask_b32_e32
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; SI: buffer_store_dwordx4
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define void @select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, i32 %c) nounwind {
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define void @s_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, i32 %c) nounwind {
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%cmp = icmp eq i32 %c, 0
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%select = select i1 %cmp, <4 x i32> %a, <4 x i32> %b
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store <4 x i32> %select, <4 x i32> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}v_select_v4i32:
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; SI: buffer_load_dwordx4
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; SI: v_cmp_gt_u32_e64 vcc, 32, s{{[0-9]+}}
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; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
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; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
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; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
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; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
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; SI: buffer_store_dwordx4
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define void @v_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %cond) #0 {
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bb:
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%tmp2 = icmp ult i32 %cond, 32
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%val = load <4 x i32>, <4 x i32> addrspace(1)* %in
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%tmp3 = select i1 %tmp2, <4 x i32> %val, <4 x i32> zeroinitializer
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store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}select_v8i32:
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; SI: v_cndmask_b32_e32
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; SI: v_cndmask_b32_e32
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@ -69,24 +89,61 @@ define void @select_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32>
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ret void
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}
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; FUNC-LABEL: {{^}}select_v2f32:
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; FUNC-LABEL: {{^}}s_select_v2f32:
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; SI-DAG: s_load_dwordx2 s{{\[}}[[ALO:[0-9]+]]:[[AHI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
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; SI-DAG: s_load_dwordx2 s{{\[}}[[BLO:[0-9]+]]:[[BHI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xd|0x34}}
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; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[ALO]]
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; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[AHI]]
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; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BLO]]
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; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BHI]]
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; SI-DAG: v_cmp_eq_i32_e64 vcc, 0, s{{[0-9]+}}
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; SI: v_cndmask_b32_e32
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; SI: v_cndmask_b32_e32
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; SI: buffer_store_dwordx2
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define void @select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b, i32 %c) nounwind {
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define void @s_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b, i32 %c) nounwind {
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%cmp = icmp eq i32 %c, 0
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%select = select i1 %cmp, <2 x float> %a, <2 x float> %b
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store <2 x float> %select, <2 x float> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}select_v4f32:
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; FUNC-LABEL: {{^}}s_select_v4f32:
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; SI: s_load_dwordx4
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; SI: s_load_dwordx4
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; SI: v_cmp_eq_i32_e64 vcc, 0, s{{[0-9]+}}
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; SI: v_cndmask_b32_e32
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; SI: v_cndmask_b32_e32
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; SI: v_cndmask_b32_e32
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; SI: v_cndmask_b32_e32
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; SI: buffer_store_dwordx4
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define void @select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b, i32 %c) nounwind {
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define void @s_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b, i32 %c) nounwind {
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%cmp = icmp eq i32 %c, 0
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%select = select i1 %cmp, <4 x float> %a, <4 x float> %b
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store <4 x float> %select, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}v_select_v4f32:
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; SI: buffer_load_dwordx4
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; SI: v_cmp_gt_u32_e64 vcc, 32, s{{[0-9]+}}
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; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
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; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
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; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
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; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
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; SI: buffer_store_dwordx4
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define void @v_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in, i32 %cond) #0 {
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bb:
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%tmp2 = icmp ult i32 %cond, 32
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%val = load <4 x float>, <4 x float> addrspace(1)* %in
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%tmp3 = select i1 %tmp2, <4 x float> %val, <4 x float> zeroinitializer
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store <4 x float> %tmp3, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}select_v8f32:
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; SI: v_cndmask_b32_e32
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; SI: v_cndmask_b32_e32
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@ -154,3 +211,9 @@ define void @select_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, <8 x
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store <8 x double> %select, <8 x double> addrspace(1)* %out, align 16
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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