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[SystemZ] Tweak SystemZInstrInfo::isBranch() interface
This is needed for the upcoming compare-and-branch patch. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182762 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -124,19 +124,18 @@ bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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// A terminator that isn't a branch can't easily be handled by this
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// analysis.
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unsigned ThisCond;
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const MachineOperand *ThisTarget;
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if (!isBranch(I, ThisCond, ThisTarget))
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if (!I->isBranch())
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return true;
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// Can't handle indirect branches.
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if (!ThisTarget->isMBB())
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SystemZII::Branch Branch(getBranchInfo(I));
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if (!Branch.Target->isMBB())
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return true;
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if (ThisCond == SystemZ::CCMASK_ANY) {
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if (Branch.CCMask == SystemZ::CCMASK_ANY) {
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// Handle unconditional branches.
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if (!AllowModify) {
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TBB = ThisTarget->getMBB();
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TBB = Branch.Target->getMBB();
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continue;
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}
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@ -148,7 +147,7 @@ bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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FBB = 0;
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// Delete the JMP if it's equivalent to a fall-through.
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if (MBB.isLayoutSuccessor(ThisTarget->getMBB())) {
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if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
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TBB = 0;
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I->eraseFromParent();
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I = MBB.end();
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@ -156,7 +155,7 @@ bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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}
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// TBB is used to indicate the unconditinal destination.
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TBB = ThisTarget->getMBB();
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TBB = Branch.Target->getMBB();
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continue;
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}
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@ -164,8 +163,8 @@ bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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if (Cond.empty()) {
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// FIXME: add X86-style branch swap
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FBB = TBB;
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TBB = ThisTarget->getMBB();
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Cond.push_back(MachineOperand::CreateImm(ThisCond));
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TBB = Branch.Target->getMBB();
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Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
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continue;
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}
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@ -175,12 +174,12 @@ bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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// Only handle the case where all conditional branches branch to the same
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// destination.
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if (TBB != ThisTarget->getMBB())
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if (TBB != Branch.Target->getMBB())
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return true;
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// If the conditions are the same, we can leave them alone.
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unsigned OldCond = Cond[0].getImm();
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if (OldCond == ThisCond)
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if (OldCond == Branch.CCMask)
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continue;
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// FIXME: Try combining conditions like X86 does. Should be easy on Z!
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@ -198,11 +197,9 @@ unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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--I;
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if (I->isDebugValue())
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continue;
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unsigned Cond;
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const MachineOperand *Target;
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if (!isBranch(I, Cond, Target))
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if (!I->isBranch())
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break;
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if (!Target->isMBB())
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if (!getBranchInfo(I).Target->isMBB())
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break;
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// Remove the branch.
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I->eraseFromParent();
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@ -358,25 +355,20 @@ uint64_t SystemZInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
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return MI->getDesc().getSize();
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}
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bool SystemZInstrInfo::isBranch(const MachineInstr *MI, unsigned &Cond,
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const MachineOperand *&Target) const {
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SystemZII::Branch
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SystemZInstrInfo::getBranchInfo(const MachineInstr *MI) const {
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switch (MI->getOpcode()) {
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case SystemZ::BR:
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case SystemZ::J:
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case SystemZ::JG:
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Cond = SystemZ::CCMASK_ANY;
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Target = &MI->getOperand(0);
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return true;
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return SystemZII::Branch(SystemZ::CCMASK_ANY, &MI->getOperand(0));
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case SystemZ::BRC:
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case SystemZ::BRCL:
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Cond = MI->getOperand(0).getImm();
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Target = &MI->getOperand(1);
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return true;
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return SystemZII::Branch(MI->getOperand(0).getImm(), &MI->getOperand(1));
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default:
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assert(!MI->getDesc().isBranch() && "Unknown branch opcode");
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return false;
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llvm_unreachable("Unrecognized branch opcode");
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}
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}
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@ -42,6 +42,17 @@ namespace SystemZII {
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// @GOT (aka @GOTENT)
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MO_GOT = (1 << 0)
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};
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// Information about a branch instruction.
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struct Branch {
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// CCMASK_<N> is set if the branch should be taken when CC == N.
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unsigned CCMask;
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// The target of the branch.
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const MachineOperand *Target;
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Branch(unsigned ccMask, const MachineOperand *target)
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: CCMask(ccMask), Target(target) {}
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};
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}
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class SystemZInstrInfo : public SystemZGenInstrInfo {
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@ -101,8 +112,7 @@ public:
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// values on which the instruction will branch, and set Target
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// to the operand that contains the branch target. This target
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// can be a register or a basic block.
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bool isBranch(const MachineInstr *MI, unsigned &Cond,
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const MachineOperand *&Target) const;
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SystemZII::Branch getBranchInfo(const MachineInstr *MI) const;
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// Get the load and store opcodes for a given register class.
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void getLoadStoreOpcodes(const TargetRegisterClass *RC,
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@ -211,22 +211,21 @@ TerminatorInfo SystemZLongBranch::describeTerminator(MachineInstr *MI) {
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TerminatorInfo Terminator;
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Terminator.Size = TII->getInstSizeInBytes(MI);
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if (MI->isConditionalBranch() || MI->isUnconditionalBranch()) {
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Terminator.Branch = MI;
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switch (MI->getOpcode()) {
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case SystemZ::J:
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// Relaxes to JG, which is 2 bytes longer.
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Terminator.TargetBlock = MI->getOperand(0).getMBB()->getNumber();
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Terminator.ExtraRelaxSize = 2;
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break;
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case SystemZ::BRC:
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// Relaxes to BRCL, which is 2 bytes longer. Operand 0 is the
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// condition code mask.
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Terminator.TargetBlock = MI->getOperand(1).getMBB()->getNumber();
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// Relaxes to BRCL, which is 2 bytes longer.
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Terminator.ExtraRelaxSize = 2;
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break;
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default:
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llvm_unreachable("Unrecognized branch instruction");
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}
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Terminator.Branch = MI;
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Terminator.TargetBlock =
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TII->getBranchInfo(MI).Target->getMBB()->getNumber();
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}
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return Terminator;
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}
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