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Move some of the InlineSpiller rematerialization code into LiveRangeEdit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116951 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -49,10 +49,7 @@ class InlineSpiller : public Spiller {
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const TargetRegisterClass *rc_;
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int stackSlot_;
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// Values of the current interval that can potentially remat.
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SmallPtrSet<VNInfo*, 8> reMattable_;
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// Values in reMattable_ that failed to remat at some point.
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// Values that failed to remat at some point.
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SmallPtrSet<VNInfo*, 8> usedValues_;
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~InlineSpiller() {}
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@ -136,6 +133,7 @@ bool InlineSpiller::split() {
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bool InlineSpiller::reMaterializeFor(MachineBasicBlock::iterator MI) {
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SlotIndex UseIdx = lis_.getInstructionIndex(MI).getUseIndex();
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VNInfo *OrigVNI = edit_->getParent().getVNInfoAt(UseIdx);
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if (!OrigVNI) {
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DEBUG(dbgs() << "\tadding <undef> flags: ");
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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@ -146,20 +144,17 @@ bool InlineSpiller::reMaterializeFor(MachineBasicBlock::iterator MI) {
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DEBUG(dbgs() << UseIdx << '\t' << *MI);
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return true;
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}
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if (!reMattable_.count(OrigVNI)) {
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DEBUG(dbgs() << "\tusing non-remat valno " << OrigVNI->id << ": "
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<< UseIdx << '\t' << *MI);
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return false;
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}
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MachineInstr *OrigMI = lis_.getInstructionFromIndex(OrigVNI->def);
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if (!edit_->allUsesAvailableAt(OrigMI, OrigVNI->def, UseIdx, lis_)) {
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LiveRangeEdit::Remat RM = edit_->canRematerializeAt(OrigVNI, UseIdx, false,
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lis_);
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if (!RM) {
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usedValues_.insert(OrigVNI);
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DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
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return false;
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}
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// If the instruction also writes edit_->getReg(), it had better not require the same
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// register for uses and defs.
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// If the instruction also writes edit_->getReg(), it had better not require
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// the same register for uses and defs.
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bool Reads, Writes;
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SmallVector<unsigned, 8> Ops;
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tie(Reads, Writes) = MI->readsWritesVirtualRegister(edit_->getReg(), &Ops);
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@ -179,11 +174,9 @@ bool InlineSpiller::reMaterializeFor(MachineBasicBlock::iterator MI) {
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NewLI.markNotSpillable();
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// Finally we can rematerialize OrigMI before MI.
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MachineBasicBlock &MBB = *MI->getParent();
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tii_.reMaterialize(MBB, MI, NewLI.reg, 0, OrigMI, tri_);
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MachineBasicBlock::iterator RematMI = MI;
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SlotIndex DefIdx = lis_.InsertMachineInstrInMaps(--RematMI).getDefIndex();
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DEBUG(dbgs() << "\tremat: " << DefIdx << '\t' << *RematMI);
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SlotIndex DefIdx = edit_->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM,
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lis_, tii_, tri_);
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DEBUG(dbgs() << "\tremat: " << DefIdx << '\n');
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// Replace operands
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for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
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@ -205,23 +198,11 @@ bool InlineSpiller::reMaterializeFor(MachineBasicBlock::iterator MI) {
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/// and trim the live ranges after.
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void InlineSpiller::reMaterializeAll() {
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// Do a quick scan of the interval values to find if any are remattable.
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reMattable_.clear();
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usedValues_.clear();
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for (LiveInterval::const_vni_iterator I = edit_->getParent().vni_begin(),
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E = edit_->getParent().vni_end(); I != E; ++I) {
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VNInfo *VNI = *I;
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if (VNI->isUnused())
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continue;
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MachineInstr *DefMI = lis_.getInstructionFromIndex(VNI->def);
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if (!DefMI || !tii_.isTriviallyReMaterializable(DefMI))
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continue;
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reMattable_.insert(VNI);
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}
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// Often, no defs are remattable.
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if (reMattable_.empty())
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if (!edit_->anyRematerializable(lis_, tii_, 0))
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return;
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usedValues_.clear();
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// Try to remat before all uses of edit_->getReg().
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bool anyRemat = false;
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for (MachineRegisterInfo::use_nodbg_iterator
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@ -234,10 +215,11 @@ void InlineSpiller::reMaterializeAll() {
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// Remove any values that were completely rematted.
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bool anyRemoved = false;
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for (SmallPtrSet<VNInfo*, 8>::iterator I = reMattable_.begin(),
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E = reMattable_.end(); I != E; ++I) {
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for (LiveInterval::vni_iterator I = edit_->getParent().vni_begin(),
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E = edit_->getParent().vni_end(); I != E; ++I) {
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VNInfo *VNI = *I;
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if (VNI->hasPHIKill() || usedValues_.count(VNI))
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if (VNI->hasPHIKill() || !edit_->didRematerialize(VNI) ||
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usedValues_.count(VNI))
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continue;
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MachineInstr *DefMI = lis_.getInstructionFromIndex(VNI->def);
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DEBUG(dbgs() << "\tremoving dead def: " << VNI->def << '\t' << *DefMI);
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@ -15,6 +15,7 @@
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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@ -38,6 +39,31 @@ LiveInterval &LiveRangeEdit::create(MachineRegisterInfo &mri,
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return li;
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}
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void LiveRangeEdit::scanRemattable(LiveIntervals &lis,
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const TargetInstrInfo &tii,
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AliasAnalysis *aa) {
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for (LiveInterval::vni_iterator I = parent_.vni_begin(),
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E = parent_.vni_end(); I != E; ++I) {
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VNInfo *VNI = *I;
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if (VNI->isUnused())
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continue;
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MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def);
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if (!DefMI)
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continue;
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if (tii.isTriviallyReMaterializable(DefMI, aa))
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remattable_.insert(VNI);
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}
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scannedRemattable_ = true;
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}
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bool LiveRangeEdit::anyRematerializable(LiveIntervals &lis,
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const TargetInstrInfo &tii,
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AliasAnalysis *aa) {
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if (!scannedRemattable_)
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scanRemattable(lis, tii, aa);
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return !remattable_.empty();
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}
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/// allUsesAvailableAt - Return true if all registers used by OrigMI at
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/// OrigIdx are also available with the same value at UseIdx.
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bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
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@ -71,3 +97,47 @@ bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
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return true;
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}
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LiveRangeEdit::Remat LiveRangeEdit::canRematerializeAt(VNInfo *ParentVNI,
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SlotIndex UseIdx,
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bool cheapAsAMove,
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LiveIntervals &lis) {
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assert(scannedRemattable_ && "Call anyRematerializable first");
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Remat RM = { 0, 0 };
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// We could remat an undefined value as IMPLICIT_DEF, but all that should have
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// been taken care of earlier.
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if (!(RM.ParentVNI = parent_.getVNInfoAt(UseIdx)))
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return RM;
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// Use scanRemattable info.
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if (!remattable_.count(RM.ParentVNI))
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return RM;
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// No defining instruction.
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MachineInstr *OrigMI = lis.getInstructionFromIndex(RM.ParentVNI->def);
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assert(OrigMI && "Defining instruction for remattable value disappeared");
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// If only cheap remats were requested, bail out early.
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if (cheapAsAMove && !OrigMI->getDesc().isAsCheapAsAMove())
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return RM;
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// Verify that all used registers are available with the same values.
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if (!allUsesAvailableAt(OrigMI, RM.ParentVNI->def, UseIdx, lis))
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return RM;
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RM.OrigMI = OrigMI;
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return RM;
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}
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SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg,
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const Remat &RM,
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LiveIntervals &lis,
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const TargetInstrInfo &tii,
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const TargetRegisterInfo &tri) {
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assert(RM.OrigMI && "Invalid remat");
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tii.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
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return lis.InsertMachineInstrInMaps(--MI).getDefIndex();
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}
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@ -19,9 +19,11 @@
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#define LLVM_CODEGEN_LIVERANGEEDIT_H
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/ADT/SmallPtrSet.h"
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namespace llvm {
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class AliasAnalysis;
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class LiveIntervals;
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class MachineRegisterInfo;
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class VirtRegMap;
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@ -34,6 +36,27 @@ class LiveRangeEdit {
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/// firstNew_ - Index of the first register added to newRegs_.
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const unsigned firstNew_;
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/// scannedRemattable_ - true when remattable values have been identified.
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bool scannedRemattable_;
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/// remattable_ - Values defined by remattable instructions as identified by
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/// tii.isTriviallyReMaterializable().
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SmallPtrSet<VNInfo*,4> remattable_;
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/// rematted_ - Values that were actually rematted, and so need to have their
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/// live range trimmed or entirely removed.
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SmallPtrSet<VNInfo*,4> rematted_;
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/// scanRemattable - Identify the parent_ values that may rematerialize.
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void scanRemattable(LiveIntervals &lis,
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const TargetInstrInfo &tii,
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AliasAnalysis *aa);
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/// allUsesAvailableAt - Return true if all registers used by OrigMI at
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/// OrigIdx are also available with the same value at UseIdx.
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bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
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SlotIndex UseIdx, LiveIntervals &lis);
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public:
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/// Create a LiveRangeEdit for breaking down parent into smaller pieces.
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/// @param parent The register being spilled or split.
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@ -45,7 +68,7 @@ public:
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SmallVectorImpl<LiveInterval*> &newRegs,
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const SmallVectorImpl<LiveInterval*> &uselessRegs)
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: parent_(parent), newRegs_(newRegs), uselessRegs_(uselessRegs),
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firstNew_(newRegs.size()) {}
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firstNew_(newRegs.size()), scannedRemattable_(false) {}
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LiveInterval &getParent() const { return parent_; }
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unsigned getReg() const { return parent_.reg; }
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@ -63,11 +86,43 @@ public:
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/// parent.
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LiveInterval &create(MachineRegisterInfo&, LiveIntervals&, VirtRegMap&);
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/// allUsesAvailableAt - Return true if all registers used by OrigMI at
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/// OrigIdx are also available with the same value at UseIdx.
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bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
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SlotIndex UseIdx, LiveIntervals &lis);
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/// anyRematerializable - Return true if any parent values may be
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/// rematerializable.
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/// This function must be called before ny rematerialization is attempted.
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bool anyRematerializable(LiveIntervals&, const TargetInstrInfo&,
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AliasAnalysis*);
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/// Remat - Information needed to rematerialize at a specific location.
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struct Remat {
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VNInfo *ParentVNI; // parent_'s value at the remat location.
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MachineInstr *OrigMI; // Instruction defining ParentVNI.
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operator bool() const { return OrigMI; }
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};
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/// canRematerializeAt - Determine if ParentVNI can be rematerialized at
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/// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI.
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/// When cheapAsAMove is set, only cheap remats are allowed.
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Remat canRematerializeAt(VNInfo *ParentVNI,
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SlotIndex UseIdx,
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bool cheapAsAMove,
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LiveIntervals &lis);
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/// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an
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/// instruction into MBB before MI. The new instruction is mapped, but
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/// liveness is not updated.
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/// Return the SlotIndex of the new instruction.
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SlotIndex rematerializeAt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg,
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const Remat &RM,
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LiveIntervals&,
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const TargetInstrInfo&,
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const TargetRegisterInfo&);
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/// didRematerialize - Return true if ParentVNI was rematerialized anywhere.
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bool didRematerialize(VNInfo *ParentVNI) const {
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return rematted_.count(ParentVNI);
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}
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};
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}
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