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Fix double FGETSIGN to work on x86_32; followup to 132396.

Browse Source 
rdar://problem/5660695


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132411 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Stuart Hastings 2011-06-01 18:32:25 +00:00
parent a3d91cd6a6
commit 090bf19de6
1 changed files with 6 additions and 3 deletions
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9
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -1759,11 +1759,14 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
Op.getOperand(0).getValueType().isFloatingPoint() && Op.getOperand(0).getValueType().isFloatingPoint() &&
!Op.getOperand(0).getValueType().isVector()) { !Op.getOperand(0).getValueType().isVector()) {
if (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) { if (isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32)) {
EVT Ty = (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) ?
Op.getValueType() : MVT::i32;
// Make a FGETSIGN + SHL to move the sign bit into the appropriate // Make a FGETSIGN + SHL to move the sign bit into the appropriate
// place. We expect the SHL to be eliminated by other optimizations. // place. We expect the SHL to be eliminated by other optimizations.
SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Op.getValueType(), SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
Op.getOperand(0)); if (Ty != Op.getValueType())
Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
unsigned ShVal = Op.getValueType().getSizeInBits()-1; unsigned ShVal = Op.getValueType().getSizeInBits()-1;
SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,