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R600: Constraints input regs of interp_xy,_zw

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183106 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune 2013-06-03 15:44:16 +00:00
parent 3e1d45bf44
commit 0962e147a4
2 changed files with 15 additions and 11 deletions
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22
lib/Target/R600/R600ISelLowering.cpp
View File

@ -543,21 +543,25 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
DL, MVT::f32, SDValue(interp, 0));
}
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &MRI = MF.getRegInfo();
unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb);
unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1);
MRI.addLiveIn(RegisterI);
MRI.addLiveIn(RegisterJ);
SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(),
SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32);
SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(),
SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32);
if (slot % 4 < 2)
interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1), MVT::f32),
CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb), MVT::f32));
RegisterJNode, RegisterINode);
else
interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1), MVT::f32),
CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb), MVT::f32));
RegisterJNode, RegisterINode);
return SDValue(interp, slot % 2);
}
case AMDGPUIntrinsic::R600_tex:

4
lib/Target/R600/R600Instructions.td
View File

@ -578,13 +578,13 @@ def isR600toCayman : Predicate<
def INTERP_PAIR_XY : AMDGPUShaderInst <
(outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),
(ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
(ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
"INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
[]>;
def INTERP_PAIR_ZW : AMDGPUShaderInst <
(outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),
(ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
(ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
"INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
[]>;