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Add shift and rotate by 1 instructions / patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28980 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
a8e83ec8c3
commit
09c545790d
@ -1394,6 +1394,14 @@ def SHL32ri : Ii8<0xC1, MRM4r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
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[(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
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}
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// Shift left by one. Not used because (add x, x) is slightly cheaper.
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def SHL8r1 : I<0xD0, MRM4r, (ops GR8 :$dst, GR8 :$src1),
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"shl{b} {$dst|$dst}", []>;
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def SHL16r1 : I<0xD1, MRM4r, (ops GR16:$dst, GR16:$src1),
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"shl{w} {$dst|$dst}", []>, OpSize;
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def SHL32r1 : I<0xD1, MRM4r, (ops GR32:$dst, GR32:$src1),
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"shl{l} {$dst|$dst}", []>;
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let isTwoAddress = 0 in {
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def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst),
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"shl{b} {%cl, $dst|$dst, %CL}",
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@ -1417,6 +1425,18 @@ let isTwoAddress = 0 in {
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def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src),
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"shl{l} {$src, $dst|$dst, $src}",
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[(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
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// Shift by 1
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def SHL8m1 : I<0xD0, MRM4m, (ops i8mem :$dst),
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"shl{b} $dst",
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[(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
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def SHL16m1 : I<0xD1, MRM4m, (ops i16mem:$dst),
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"shl{w} $dst",
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[(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
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OpSize;
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def SHL32m1 : I<0xD1, MRM4m, (ops i32mem:$dst),
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"shl{l} $dst",
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[(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
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}
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def SHR8rCL : I<0xD2, MRM5r, (ops GR8 :$dst, GR8 :$src),
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@ -1439,6 +1459,17 @@ def SHR32ri : Ii8<0xC1, MRM5r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
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"shr{l} {$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
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// Shift by 1
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def SHR8r1 : I<0xD0, MRM5r, (ops GR8:$dst, GR8:$src1),
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"shr{b} $dst",
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[(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
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def SHR16r1 : I<0xD1, MRM5r, (ops GR16:$dst, GR16:$src1),
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"shr{w} $dst",
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[(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
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def SHR32r1 : I<0xD1, MRM5r, (ops GR32:$dst, GR32:$src1),
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"shr{l} $dst",
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[(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
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let isTwoAddress = 0 in {
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def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst),
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"shr{b} {%cl, $dst|$dst, %CL}",
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@ -1462,6 +1493,17 @@ let isTwoAddress = 0 in {
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def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src),
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"shr{l} {$src, $dst|$dst, $src}",
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[(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
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// Shift by 1
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def SHR8m1 : I<0xD0, MRM5m, (ops i8mem :$dst),
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"shr{b} $dst",
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[(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
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def SHR16m1 : I<0xD1, MRM5m, (ops i16mem:$dst),
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"shr{w} $dst",
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[(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
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def SHR32m1 : I<0xD1, MRM5m, (ops i32mem:$dst),
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"shr{l} $dst",
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[(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
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}
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def SAR8rCL : I<0xD2, MRM7r, (ops GR8 :$dst, GR8 :$src),
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@ -1484,6 +1526,18 @@ def SAR16ri : Ii8<0xC1, MRM7r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
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def SAR32ri : Ii8<0xC1, MRM7r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
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"sar{l} {$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
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// Shift by 1
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def SAR8r1 : I<0xD0, MRM7r, (ops GR8 :$dst, GR8 :$src1),
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"sar{b} $dst",
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[(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
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def SAR16r1 : I<0xD1, MRM7r, (ops GR16:$dst, GR16:$src1),
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"sar{w} $dst",
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[(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
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def SAR32r1 : I<0xD1, MRM7r, (ops GR32:$dst, GR32:$src1),
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"sar{l} $dst",
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[(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
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let isTwoAddress = 0 in {
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def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst),
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"sar{b} {%cl, $dst|$dst, %CL}",
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@ -1507,6 +1561,18 @@ let isTwoAddress = 0 in {
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def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src),
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"sar{l} {$src, $dst|$dst, $src}",
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[(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
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// Shift by 1
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def SAR8m1 : I<0xD0, MRM7m, (ops i8mem :$dst),
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"sar{b} $dst",
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[(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
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def SAR16m1 : I<0xD1, MRM7m, (ops i16mem:$dst),
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"sar{w} $dst",
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[(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
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OpSize;
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def SAR32m1 : I<0xD1, MRM7m, (ops i32mem:$dst),
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"sar{l} $dst",
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[(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
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}
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// Rotate instructions
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@ -1531,6 +1597,17 @@ def ROL32ri : Ii8<0xC1, MRM0r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
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"rol{l} {$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
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// Rotate by 1
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def ROL8r1 : I<0xD0, MRM0r, (ops GR8 :$dst, GR8 :$src1),
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"rol{b} $dst",
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[(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
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def ROL16r1 : I<0xD1, MRM0r, (ops GR16:$dst, GR16:$src1),
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"rol{w} $dst",
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[(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
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def ROL32r1 : I<0xD1, MRM0r, (ops GR32:$dst, GR32:$src1),
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"rol{l} $dst",
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[(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
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let isTwoAddress = 0 in {
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def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst),
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"rol{b} {%cl, $dst|$dst, %CL}",
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@ -1554,6 +1631,18 @@ let isTwoAddress = 0 in {
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def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src),
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"rol{l} {$src, $dst|$dst, $src}",
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[(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
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// Rotate by 1
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def ROL8m1 : I<0xD0, MRM0m, (ops i8mem :$dst),
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"rol{b} $dst",
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[(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
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def ROL16m1 : I<0xD1, MRM0m, (ops i16mem:$dst),
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"rol{w} $dst",
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[(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
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OpSize;
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def ROL32m1 : I<0xD1, MRM0m, (ops i32mem:$dst),
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"rol{l} $dst",
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[(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
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}
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def ROR8rCL : I<0xD2, MRM1r, (ops GR8 :$dst, GR8 :$src),
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@ -1575,6 +1664,18 @@ def ROR16ri : Ii8<0xC1, MRM1r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
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def ROR32ri : Ii8<0xC1, MRM1r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
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"ror{l} {$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
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// Rotate by 1
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def ROR8r1 : I<0xD0, MRM1r, (ops GR8 :$dst, GR8 :$src1),
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"ror{b} $dst",
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[(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
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def ROR16r1 : I<0xD1, MRM1r, (ops GR16:$dst, GR16:$src1),
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"ror{w} $dst",
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[(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
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def ROR32r1 : I<0xD1, MRM1r, (ops GR32:$dst, GR32:$src1),
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"ror{l} $dst",
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[(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
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let isTwoAddress = 0 in {
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def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst),
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"ror{b} {%cl, $dst|$dst, %CL}",
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@ -1598,6 +1699,18 @@ let isTwoAddress = 0 in {
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def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src),
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"ror{l} {$src, $dst|$dst, $src}",
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[(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
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// Rotate by 1
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def ROR8m1 : I<0xD0, MRM1m, (ops i8mem :$dst),
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"ror{b} $dst",
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[(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
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def ROR16m1 : I<0xD1, MRM1m, (ops i16mem:$dst),
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"ror{w} $dst",
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[(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
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OpSize;
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def ROR32m1 : I<0xD1, MRM1m, (ops i32mem:$dst),
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"ror{l} $dst",
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[(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
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}
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@ -288,30 +288,45 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
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case X86::SHL8ri: return MakeMIInst(X86::SHL8mi , FrameIndex, MI);
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case X86::SHL16ri: return MakeMIInst(X86::SHL16mi, FrameIndex, MI);
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case X86::SHL32ri: return MakeMIInst(X86::SHL32mi, FrameIndex, MI);
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case X86::SHL8r1: return MakeMInst(X86::SHL8m1 , FrameIndex, MI);
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case X86::SHL16r1: return MakeMInst(X86::SHL16m1, FrameIndex, MI);
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case X86::SHL32r1: return MakeMInst(X86::SHL32m1, FrameIndex, MI);
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case X86::SHR8rCL: return MakeMInst( X86::SHR8mCL ,FrameIndex, MI);
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case X86::SHR16rCL: return MakeMInst( X86::SHR16mCL,FrameIndex, MI);
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case X86::SHR32rCL: return MakeMInst( X86::SHR32mCL,FrameIndex, MI);
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case X86::SHR8ri: return MakeMIInst(X86::SHR8mi , FrameIndex, MI);
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case X86::SHR16ri: return MakeMIInst(X86::SHR16mi, FrameIndex, MI);
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case X86::SHR32ri: return MakeMIInst(X86::SHR32mi, FrameIndex, MI);
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case X86::SHR8r1: return MakeMInst(X86::SHR8m1 , FrameIndex, MI);
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case X86::SHR16r1: return MakeMInst(X86::SHR16m1, FrameIndex, MI);
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case X86::SHR32r1: return MakeMInst(X86::SHR32m1, FrameIndex, MI);
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case X86::SAR8rCL: return MakeMInst( X86::SAR8mCL ,FrameIndex, MI);
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case X86::SAR16rCL: return MakeMInst( X86::SAR16mCL,FrameIndex, MI);
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case X86::SAR32rCL: return MakeMInst( X86::SAR32mCL,FrameIndex, MI);
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case X86::SAR8ri: return MakeMIInst(X86::SAR8mi , FrameIndex, MI);
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case X86::SAR16ri: return MakeMIInst(X86::SAR16mi, FrameIndex, MI);
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case X86::SAR32ri: return MakeMIInst(X86::SAR32mi, FrameIndex, MI);
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case X86::SAR8r1: return MakeMInst(X86::SAR8m1 , FrameIndex, MI);
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case X86::SAR16r1: return MakeMInst(X86::SAR16m1, FrameIndex, MI);
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case X86::SAR32r1: return MakeMInst(X86::SAR32m1, FrameIndex, MI);
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case X86::ROL8rCL: return MakeMInst( X86::ROL8mCL ,FrameIndex, MI);
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case X86::ROL16rCL: return MakeMInst( X86::ROL16mCL,FrameIndex, MI);
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case X86::ROL32rCL: return MakeMInst( X86::ROL32mCL,FrameIndex, MI);
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case X86::ROL8ri: return MakeMIInst(X86::ROL8mi , FrameIndex, MI);
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case X86::ROL16ri: return MakeMIInst(X86::ROL16mi, FrameIndex, MI);
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case X86::ROL32ri: return MakeMIInst(X86::ROL32mi, FrameIndex, MI);
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case X86::ROL8r1: return MakeMInst(X86::ROL8m1 , FrameIndex, MI);
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case X86::ROL16r1: return MakeMInst(X86::ROL16m1, FrameIndex, MI);
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case X86::ROL32r1: return MakeMInst(X86::ROL32m1, FrameIndex, MI);
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case X86::ROR8rCL: return MakeMInst( X86::ROR8mCL ,FrameIndex, MI);
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case X86::ROR16rCL: return MakeMInst( X86::ROR16mCL,FrameIndex, MI);
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case X86::ROR32rCL: return MakeMInst( X86::ROR32mCL,FrameIndex, MI);
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case X86::ROR8ri: return MakeMIInst(X86::ROR8mi , FrameIndex, MI);
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case X86::ROR16ri: return MakeMIInst(X86::ROR16mi, FrameIndex, MI);
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case X86::ROR32ri: return MakeMIInst(X86::ROR32mi, FrameIndex, MI);
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case X86::ROR8r1: return MakeMInst(X86::ROR8m1 , FrameIndex, MI);
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case X86::ROR16r1: return MakeMInst(X86::ROR16m1, FrameIndex, MI);
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case X86::ROR32r1: return MakeMInst(X86::ROR32m1, FrameIndex, MI);
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case X86::SHLD32rrCL:return MakeMRInst( X86::SHLD32mrCL,FrameIndex, MI);
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case X86::SHLD32rri8:return MakeMRIInst(X86::SHLD32mri8,FrameIndex, MI);
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case X86::SHRD32rrCL:return MakeMRInst( X86::SHRD32mrCL,FrameIndex, MI);
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