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Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74158 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-06-25 02:08:06 +00:00
parent df5a7daff9
commit 0aa1d8c52d
2 changed files with 140 additions and 111 deletions
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47
lib/Target/ARM/ARMInstrFormats.td
View File

@ -773,20 +773,51 @@ class Thumb1Pat<dag pattern, dag result> : Pat<pattern, result> {
list<Predicate> Predicates = [IsThumb1Only]; list<Predicate> Predicates = [IsThumb1Only];
} }
// T2I - Thumb2 instruction. // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
class Thumb2I<dag outs, dag ins, AddrMode am, SizeFlagVal sz, string opc, string asm, string cstr, list<dag> pattern>
string asm, string cstr, list<dag> pattern>
: InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> { : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> {
let OutOperandList = outs; let OutOperandList = oops;
let InOperandList = ins; let InOperandList = !con(iops, (ops pred:$p));
let AsmString = !strconcat(opc, !strconcat("${p}", asm));
let Pattern = pattern;
list<Predicate> Predicates = [IsThumb, HasThumb2];
}
// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as
// an input operand since by default it's a zero register. It will
// become an implicit def once it's "flipped".
// FIXME: This uses unified syntax so {s} comes before {p}. We should make it
// more consistent.
class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
string opc, string asm, string cstr, list<dag> pattern>
: InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> {
let OutOperandList = oops;
let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
let Pattern = pattern;
list<Predicate> Predicates = [IsThumb, HasThumb2];
}
// Special cases
class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
string asm, string cstr, list<dag> pattern>
: InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> {
let OutOperandList = oops;
let InOperandList = iops;
let AsmString = asm; let AsmString = asm;
let Pattern = pattern; let Pattern = pattern;
list<Predicate> Predicates = [IsThumb, HasThumb2]; list<Predicate> Predicates = [IsThumb, HasThumb2];
} }
class T2I<dag outs, dag ins, string asm, list<dag> pattern> class T2I<dag oops, dag iops, string opc, string asm, list<dag> pattern>
: Thumb2I<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>; : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, opc, asm, "", pattern>;
class T2sI<dag oops, dag iops, string opc, string asm, list<dag> pattern>
: Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, opc, asm, "", pattern>;
class T2XI<dag oops, dag iops, string asm, list<dag> pattern>
: Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, asm, "", pattern>;
// Thumb2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. // Thumb2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
class Thumb2Pat<dag pattern, dag result> : Pat<pattern, result> { class Thumb2Pat<dag pattern, dag result> : Pat<pattern, result> {

204
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -131,55 +131,57 @@ def t2_lo16AllZero : PatLeaf<(i32 imm), [{
// //
/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
// unary operation that produces a value. /// unary operation that produces a value. These are predicable and can be
/// changed to modify CPSR.
multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{ multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
// shifted imm // shifted imm
def i : T2I<(outs GPR:$dst), (ins t2_so_imm:$src), def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
!strconcat(opc, " $dst, $src"), opc, " $dst, $src",
[(set GPR:$dst, (opnode t2_so_imm:$src))]> { [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
let isAsCheapAsAMove = Cheap; let isAsCheapAsAMove = Cheap;
let isReMaterializable = ReMat; let isReMaterializable = ReMat;
} }
// register // register
def r : T2I<(outs GPR:$dst), (ins GPR:$src), def r : T2I<(outs GPR:$dst), (ins GPR:$src),
!strconcat(opc, " $dst, $src"), opc, " $dst, $src",
[(set GPR:$dst, (opnode GPR:$src))]>; [(set GPR:$dst, (opnode GPR:$src))]>;
// shifted register // shifted register
def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src),
!strconcat(opc, " $dst, $src"), opc, " $dst, $src",
[(set GPR:$dst, (opnode t2_so_reg:$src))]>; [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
} }
/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
// binary operation that produces a value. // binary operation that produces a value. These are predicable and can be
/// changed to modify CPSR.
multiclass T2I_bin_irs<string opc, PatFrag opnode> { multiclass T2I_bin_irs<string opc, PatFrag opnode> {
// shifted imm // shifted imm
def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
!strconcat(opc, " $dst, $lhs, $rhs"), opc, " $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
// register // register
def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
!strconcat(opc, " $dst, $lhs, $rhs"), opc, " $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
// shifted register // shifted register
def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
!strconcat(opc, " $dst, $lhs, $rhs"), opc, " $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
} }
/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are reversed. /// T2I_rbin_irs - Same as T2I_bin_irs except the order of operands are reversed.
multiclass T2I_rbin_irs<string opc, PatFrag opnode> { multiclass T2I_rbin_irs<string opc, PatFrag opnode> {
// shifted imm // shifted imm
def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
!strconcat(opc, " $dst, $rhs, $lhs"), opc, " $dst, $rhs, $lhs",
[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
// register // register
def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs), def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs),
!strconcat(opc, " $dst, $rhs, $lhs"), opc, " $dst, $rhs, $lhs",
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
// shifted register // shifted register
def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
!strconcat(opc, " $dst, $rhs, $lhs"), opc, " $dst, $rhs, $lhs",
[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
} }
@ -189,15 +191,15 @@ let Defs = [CPSR] in {
multiclass T2I_bin_s_irs<string opc, PatFrag opnode> { multiclass T2I_bin_s_irs<string opc, PatFrag opnode> {
// shifted imm // shifted imm
def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
!strconcat(opc, "s $dst, $lhs, $rhs"), !strconcat(opc, "s"), " $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
// register // register
def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
!strconcat(opc, " $dst, $lhs, $rhs"), !strconcat(opc, "s"), " $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
// shifted register // shifted register
def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
!strconcat(opc, "s $dst, $lhs, $rhs"), !strconcat(opc, "s"), " $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
} }
} }
@ -208,15 +210,15 @@ let Defs = [CPSR] in {
multiclass T2I_rbin_s_irs<string opc, PatFrag opnode> { multiclass T2I_rbin_s_irs<string opc, PatFrag opnode> {
// shifted imm // shifted imm
def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
!strconcat(opc, "s $dst, $rhs, $lhs"), !strconcat(opc, "s"), " $dst, $rhs, $lhs",
[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
// register // register
def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs), def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs),
!strconcat(opc, " $dst, $rhs, $lhs"), !strconcat(opc, "s"), " $dst, $rhs, $lhs",
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
// shifted register // shifted register
def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
!strconcat(opc, "s $dst, $rhs, $lhs"), !strconcat(opc, "s"), " $dst, $rhs, $lhs",
[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
} }
} }
@ -225,21 +227,21 @@ multiclass T2I_rbin_s_irs<string opc, PatFrag opnode> {
/// patterns for a binary operation that produces a value. /// patterns for a binary operation that produces a value.
multiclass T2I_bin_ii12rs<string opc, PatFrag opnode> { multiclass T2I_bin_ii12rs<string opc, PatFrag opnode> {
// shifted imm // shifted imm
def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
!strconcat(opc, " $dst, $lhs, $rhs"), opc, " $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
// 12-bit imm // 12-bit imm
def ri12 : T2I<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
!strconcat(opc, "w $dst, $lhs, $rhs"), !strconcat(opc, "w"), " $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
// register // register
def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
!strconcat(opc, " $dst, $lhs, $rhs"), opc, " $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
// shifted register // shifted register
def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
!strconcat(opc, " $dst, $lhs, $rhs"), opc, " $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
} }
/// T2I_bin_c_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a /// T2I_bin_c_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
@ -248,17 +250,17 @@ multiclass T2I_bin_ii12rs<string opc, PatFrag opnode> {
let Uses = [CPSR] in { let Uses = [CPSR] in {
multiclass T2I_bin_c_irs<string opc, PatFrag opnode> { multiclass T2I_bin_c_irs<string opc, PatFrag opnode> {
// shifted imm // shifted imm
def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs, cc_out:$s), def ri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs, cc_out:$s),
!strconcat(opc, "${s} $dst, $lhs, $rhs"), !strconcat(opc, "${s} $dst, $lhs, $rhs"),
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
// register // register
def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, cc_out:$s), def rr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, cc_out:$s),
!strconcat(opc, "${s} $dst, $lhs, $rhs"), !strconcat(opc, "${s} $dst, $lhs, $rhs"),
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
// shifted register // shifted register
def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s), def rs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s),
!strconcat(opc, "${s} $dst, $lhs, $rhs"), !strconcat(opc, "${s} $dst, $lhs, $rhs"),
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
} }
} }
@ -267,17 +269,17 @@ multiclass T2I_bin_c_irs<string opc, PatFrag opnode> {
let Uses = [CPSR] in { let Uses = [CPSR] in {
multiclass T2I_rbin_c_irs<string opc, PatFrag opnode> { multiclass T2I_rbin_c_irs<string opc, PatFrag opnode> {
// shifted imm // shifted imm
def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s), def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
!strconcat(opc, "${s} $dst, $rhs, $lhs"), !strconcat(opc, "${s} $dst, $rhs, $lhs"),
[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
// register // register
def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs, cc_out:$s), def rr : T2XI<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs, cc_out:$s),
!strconcat(opc, "${s} $dst, $rhs, $lhs"), !strconcat(opc, "${s} $dst, $rhs, $lhs"),
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
// shifted register // shifted register
def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s), def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
!strconcat(opc, "${s} $dst, $rhs, $lhs"), !strconcat(opc, "${s} $dst, $rhs, $lhs"),
[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
} }
} }
@ -285,13 +287,13 @@ multiclass T2I_rbin_c_irs<string opc, PatFrag opnode> {
// rotate operation that produces a value. // rotate operation that produces a value.
multiclass T2I_sh_ir<string opc, PatFrag opnode> { multiclass T2I_sh_ir<string opc, PatFrag opnode> {
// 5-bit imm // 5-bit imm
def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
!strconcat(opc, " $dst, $lhs, $rhs"), opc, " $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
// register // register
def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
!strconcat(opc, " $dst, $lhs, $rhs"), opc, " $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
} }
/// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test /// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
@ -301,15 +303,15 @@ let Uses = [CPSR] in {
multiclass T2I_cmp_is<string opc, PatFrag opnode> { multiclass T2I_cmp_is<string opc, PatFrag opnode> {
// shifted imm // shifted imm
def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
!strconcat(opc, " $lhs, $rhs"), opc, " $lhs, $rhs",
[(opnode GPR:$lhs, t2_so_imm:$rhs)]>; [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
// register // register
def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs),
!strconcat(opc, " $lhs, $rhs"), opc, " $lhs, $rhs",
[(opnode GPR:$lhs, GPR:$rhs)]>; [(opnode GPR:$lhs, GPR:$rhs)]>;
// shifted register // shifted register
def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
!strconcat(opc, " $lhs, $rhs"), opc, " $lhs, $rhs",
[(opnode GPR:$lhs, t2_so_reg:$rhs)]>; [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
} }
} }
@ -319,21 +321,21 @@ multiclass T2I_cmp_is<string opc, PatFrag opnode> {
// //
let isNotDuplicable = 1 in let isNotDuplicable = 1 in
def t2PICADD : T2I<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp), def t2PICADD : T2XI<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
"$cp:\n\tadd $dst, pc", "$cp:\n\tadd $dst, pc",
[(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>; [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
// LEApcrel - Load a pc-relative address into a register without offending the // LEApcrel - Load a pc-relative address into a register without offending the
// assembler. // assembler.
def t2LEApcrel : T2I<(outs GPR:$dst), (ins i32imm:$label, pred:$p), def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
!strconcat(!strconcat(".set PCRELV${:uid}, ($label-(", !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
"${:private}PCRELL${:uid}+8))\n"), "${:private}PCRELL${:uid}+8))\n"),
!strconcat("${:private}PCRELL${:uid}:\n\t", !strconcat("${:private}PCRELL${:uid}:\n\t",
"add$p $dst, pc, #PCRELV${:uid}")), "add$p $dst, pc, #PCRELV${:uid}")),
[]>; []>;
def t2LEApcrelJT : T2I<(outs GPR:$dst), def t2LEApcrelJT : T2XI<(outs GPR:$dst),
(ins i32imm:$label, i32imm:$id, pred:$p), (ins i32imm:$label, i32imm:$id, pred:$p),
!strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(", !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
"${:private}PCRELL${:uid}+8))\n"), "${:private}PCRELL${:uid}+8))\n"),
@ -342,43 +344,39 @@ def t2LEApcrelJT : T2I<(outs GPR:$dst),
[]>; []>;
// ADD rd, sp, #so_imm // ADD rd, sp, #so_imm
def t2ADDrSPi : T2I<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), def t2ADDrSPi : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
"add $dst, $sp, $imm", "add $dst, $sp, $imm",
[]>; []>;
// ADD rd, sp, #imm12 // ADD rd, sp, #imm12
def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, i32imm:$imm), def t2ADDrSPi12 : T2XI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$imm),
"addw $dst, $sp, $imm", "addw $dst, $sp, $imm",
[]>; []>;
def t2ADDrSPs : T2I<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), def t2ADDrSPs : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
"addw $dst, $sp, $rhs", "addw $dst, $sp, $rhs",
[]>; []>;
//===----------------------------------------------------------------------===//
// Arithmetic Instructions.
//
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Move Instructions. // Move Instructions.
// //
let neverHasSideEffects = 1 in let neverHasSideEffects = 1 in
def t2MOVr : T2I<(outs GPR:$dst), (ins GPR:$src), def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src),
"mov $dst, $src", []>; "mov", " $dst, $src", []>;
let isReMaterializable = 1, isAsCheapAsAMove = 1 in let isReMaterializable = 1, isAsCheapAsAMove = 1 in
def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), def t2MOVi16 : T2sI<(outs GPR:$dst), (ins i32imm:$src),
"movw $dst, $src", "movw", " $dst, $src",
[(set GPR:$dst, imm0_65535:$src)]>; [(set GPR:$dst, imm0_65535:$src)]>;
// FIXME: Also available in ARM mode. // FIXME: Also available in ARM mode.
let Constraints = "$src = $dst" in let Constraints = "$src = $dst" in
def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
"movt $dst, $imm", "movt", " $dst, $imm",
[(set GPR:$dst, [(set GPR:$dst,
(or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>; (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Arithmetic Instructions. // Arithmetic Instructions.
@ -416,9 +414,9 @@ defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>; defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>; defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
def t2MOVrx : T2I<(outs GPR:$dst), (ins GPR:$src), def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src),
"mov $dst, $src, rrx", "mov", " $dst, $src, rrx",
[(set GPR:$dst, (ARMrrx GPR:$src))]>; [(set GPR:$dst, (ARMrrx GPR:$src))]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Bitwise Instructions. // Bitwise Instructions.
@ -444,7 +442,7 @@ defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
// FIXME: Also available in ARM mode. // FIXME: Also available in ARM mode.
let Constraints = "$src = $dst" in let Constraints = "$src = $dst" in
def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
"bfc $dst, $imm", "bfc", " $dst, $imm",
[(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>; [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
// FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1) // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
@ -453,15 +451,15 @@ def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
// Multiply Instructions. // Multiply Instructions.
// //
def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
"mul $dst, $a, $b", "mul", " $dst, $a, $b",
[(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
"mla $dst, $a, $b, $c", "mla", " $dst, $a, $b, $c",
[(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
"mls $dst, $a, $b, $c", "mls", " $dst, $a, $b, $c",
[(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>; [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
// FIXME: SMULL, etc. // FIXME: SMULL, etc.
@ -475,15 +473,15 @@ def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
///// /////
// FIXME not firing? but ARM version does... // FIXME not firing? but ARM version does...
def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src), def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
"clz $dst, $src", "clz", " $dst, $src",
[(set GPR:$dst, (ctlz GPR:$src))]>; [(set GPR:$dst, (ctlz GPR:$src))]>;
def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src), def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
"rev $dst, $src", "rev", " $dst, $src",
[(set GPR:$dst, (bswap GPR:$src))]>; [(set GPR:$dst, (bswap GPR:$src))]>;
def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src), def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
"rev16 $dst, $src", "rev16", " $dst, $src",
[(set GPR:$dst, [(set GPR:$dst,
(or (and (srl GPR:$src, (i32 8)), 0xFF), (or (and (srl GPR:$src, (i32 8)), 0xFF),
(or (and (shl GPR:$src, (i32 8)), 0xFF00), (or (and (shl GPR:$src, (i32 8)), 0xFF00),
@ -494,7 +492,7 @@ def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
/// A8.6.137 REVSH /// A8.6.137 REVSH
///// /////
def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src), def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
"revsh $dst, $src", "revsh", " $dst, $src",
[(set GPR:$dst, [(set GPR:$dst,
(sext_inreg (sext_inreg
(or (srl (and GPR:$src, 0xFFFF), (i32 8)), (or (srl (and GPR:$src, 0xFFFF), (i32 8)),