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Implement vector count leading/trailing bytes with zero lsb and vector parity

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builtins - llvm portion

This patch corresponds to review https://reviews.llvm.org/D26003.
Committing on behalf of Zaara Syeda.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285434 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nemanja Ivanovic 2016-10-28 19:38:24 +00:00
parent 4c68e05037
commit 0b61b12b8c
3 changed files with 80 additions and 7 deletions
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11
include/llvm/IR/IntrinsicsPowerPC.td
View File

@ -360,6 +360,17 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
def int_ppc_altivec_vcmpnezb_p : GCCBuiltin<"__builtin_altivec_vcmpnezb_p">,
Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v16i8_ty,llvm_v16i8_ty],
[IntrNoMem]>;
def int_ppc_altivec_vclzlsbb : GCCBuiltin<"__builtin_altivec_vclzlsbb">,
Intrinsic<[llvm_i32_ty],[llvm_v16i8_ty],[IntrNoMem]>;
def int_ppc_altivec_vctzlsbb : GCCBuiltin<"__builtin_altivec_vctzlsbb">,
Intrinsic<[llvm_i32_ty],[llvm_v16i8_ty],[IntrNoMem]>;
def int_ppc_altivec_vprtybw : GCCBuiltin<"__builtin_altivec_vprtybw">,
Intrinsic<[llvm_v4i32_ty],[llvm_v4i32_ty],[IntrNoMem]>;
def int_ppc_altivec_vprtybd : GCCBuiltin<"__builtin_altivec_vprtybd">,
Intrinsic<[llvm_v2i64_ty],[llvm_v2i64_ty],[IntrNoMem]>;
def int_ppc_altivec_vprtybq : GCCBuiltin<"__builtin_altivec_vprtybq">,
Intrinsic<[llvm_v1i128_ty],[llvm_v1i128_ty],[IntrNoMem]>;
}
// Vector average.

21
lib/Target/PowerPC/PPCInstrAltivec.td
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@ -1281,10 +1281,14 @@ class VX_VT5_EO5_VB5s<bits<11> xo, bits<5> eo, string opc, list<dag> pattern>
!strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>;
// Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD]
def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs g8rc:$rD), (ins vrrc:$vB),
"vclzlsbb $rD, $vB", IIC_VecGeneral, []>;
def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs g8rc:$rD), (ins vrrc:$vB),
"vctzlsbb $rD, $vB", IIC_VecGeneral, []>;
def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs gprc:$rD), (ins vrrc:$vB),
"vclzlsbb $rD, $vB", IIC_VecGeneral,
[(set i32:$rD, (int_ppc_altivec_vclzlsbb
v16i8:$vB))]>;
def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs gprc:$rD), (ins vrrc:$vB),
"vctzlsbb $rD, $vB", IIC_VecGeneral,
[(set i32:$rD, (int_ppc_altivec_vctzlsbb
v16i8:$vB))]>;
// Vector Count Trailing Zeros
def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb",
[(set v16i8:$vD, (cttz v16i8:$vB))]>;
@ -1314,9 +1318,12 @@ def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw", []>;
def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", []>;
// Vector Parity Byte
def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", []>;
def VPRTYBD : VX_VT5_EO5_VB5<1538, 9, "vprtybd", []>;
def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", []>;
def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", [(set v4i32:$vD,
(int_ppc_altivec_vprtybw v4i32:$vB))]>;
def VPRTYBD : VX_VT5_EO5_VB5<1538, 9, "vprtybd", [(set v2i64:$vD,
(int_ppc_altivec_vprtybd v2i64:$vB))]>;
def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", [(set v1i128:$vD,
(int_ppc_altivec_vprtybq v1i128:$vB))]>;
// Vector (Bit) Permute (Right-indexed)
def VBPERMD : VXForm_1<1484, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),

55
test/CodeGen/PowerPC/p9-vector-compares-and-counts.ll
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@ -145,3 +145,58 @@ declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1)
; Function Attrs: nounwind readnone
declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1)
; Function Attrs: nounwind readnone
define i32 @testVCLZLSBB(<16 x i8> %a) {
entry:
%0 = tail call i32 @llvm.ppc.altivec.vclzlsbb(<16 x i8> %a)
ret i32 %0
; CHECK-LABEL: testVCLZLSBB
; CHECK: vclzlsbb 3, 2
}
; Function Attrs: nounwind readnone
declare i32 @llvm.ppc.altivec.vclzlsbb(<16 x i8>)
; Function Attrs: nounwind readnone
define i32 @testVCTZLSBB(<16 x i8> %a) {
entry:
%0 = tail call i32 @llvm.ppc.altivec.vctzlsbb(<16 x i8> %a)
ret i32 %0
; CHECK-LABEL: testVCTZLSBB
; CHECK: vctzlsbb 3, 2
}
; Function Attrs: nounwind readnone
declare i32 @llvm.ppc.altivec.vctzlsbb(<16 x i8>)
; Function Attrs: nounwind readnone
define <4 x i32> @testVPRTYBW(<4 x i32> %a) {
entry:
%0 = tail call <4 x i32> @llvm.ppc.altivec.vprtybw(<4 x i32> %a)
ret <4 x i32> %0
; CHECK-LABEL: testVPRTYBW
; CHECK: vprtybw 2, 2
}
; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vprtybw(<4 x i32>)
; Function Attrs: nounwind readnone
define <2 x i64> @testVPRTYBD(<2 x i64> %a) {
entry:
%0 = tail call <2 x i64> @llvm.ppc.altivec.vprtybd(<2 x i64> %a)
ret <2 x i64> %0
; CHECK-LABEL: testVPRTYBD
; CHECK: vprtybd 2, 2
}
; Function Attrs: nounwind readnone
declare <2 x i64> @llvm.ppc.altivec.vprtybd(<2 x i64>)
; Function Attrs: nounwind readnone
define <1 x i128> @testVPRTYBQ(<1 x i128> %a) {
entry:
%0 = tail call <1 x i128> @llvm.ppc.altivec.vprtybq(<1 x i128> %a)
ret <1 x i128> %0
; CHECK-LABEL: testVPRTYBQ
; CHECK: vprtybq 2, 2
}
; Function Attrs: nounwind readnone
declare <1 x i128> @llvm.ppc.altivec.vprtybq(<1 x i128>)