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Implement vector count leading/trailing bytes with zero lsb and vector parity
builtins - llvm portion This patch corresponds to review https://reviews.llvm.org/D26003. Committing on behalf of Zaara Syeda. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285434 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -360,6 +360,17 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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def int_ppc_altivec_vcmpnezb_p : GCCBuiltin<"__builtin_altivec_vcmpnezb_p">,
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def int_ppc_altivec_vcmpnezb_p : GCCBuiltin<"__builtin_altivec_vcmpnezb_p">,
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Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v16i8_ty,llvm_v16i8_ty],
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Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v16i8_ty,llvm_v16i8_ty],
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[IntrNoMem]>;
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[IntrNoMem]>;
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def int_ppc_altivec_vclzlsbb : GCCBuiltin<"__builtin_altivec_vclzlsbb">,
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Intrinsic<[llvm_i32_ty],[llvm_v16i8_ty],[IntrNoMem]>;
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def int_ppc_altivec_vctzlsbb : GCCBuiltin<"__builtin_altivec_vctzlsbb">,
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Intrinsic<[llvm_i32_ty],[llvm_v16i8_ty],[IntrNoMem]>;
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def int_ppc_altivec_vprtybw : GCCBuiltin<"__builtin_altivec_vprtybw">,
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Intrinsic<[llvm_v4i32_ty],[llvm_v4i32_ty],[IntrNoMem]>;
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def int_ppc_altivec_vprtybd : GCCBuiltin<"__builtin_altivec_vprtybd">,
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Intrinsic<[llvm_v2i64_ty],[llvm_v2i64_ty],[IntrNoMem]>;
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def int_ppc_altivec_vprtybq : GCCBuiltin<"__builtin_altivec_vprtybq">,
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Intrinsic<[llvm_v1i128_ty],[llvm_v1i128_ty],[IntrNoMem]>;
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}
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}
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// Vector average.
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// Vector average.
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@ -1281,10 +1281,14 @@ class VX_VT5_EO5_VB5s<bits<11> xo, bits<5> eo, string opc, list<dag> pattern>
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!strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>;
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!strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>;
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// Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD]
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// Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD]
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def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs g8rc:$rD), (ins vrrc:$vB),
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def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs gprc:$rD), (ins vrrc:$vB),
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"vclzlsbb $rD, $vB", IIC_VecGeneral, []>;
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"vclzlsbb $rD, $vB", IIC_VecGeneral,
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def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs g8rc:$rD), (ins vrrc:$vB),
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[(set i32:$rD, (int_ppc_altivec_vclzlsbb
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"vctzlsbb $rD, $vB", IIC_VecGeneral, []>;
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v16i8:$vB))]>;
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def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs gprc:$rD), (ins vrrc:$vB),
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"vctzlsbb $rD, $vB", IIC_VecGeneral,
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[(set i32:$rD, (int_ppc_altivec_vctzlsbb
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v16i8:$vB))]>;
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// Vector Count Trailing Zeros
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// Vector Count Trailing Zeros
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def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb",
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def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb",
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[(set v16i8:$vD, (cttz v16i8:$vB))]>;
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[(set v16i8:$vD, (cttz v16i8:$vB))]>;
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@ -1314,9 +1318,12 @@ def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw", []>;
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def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", []>;
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def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", []>;
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// Vector Parity Byte
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// Vector Parity Byte
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def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", []>;
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def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", [(set v4i32:$vD,
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def VPRTYBD : VX_VT5_EO5_VB5<1538, 9, "vprtybd", []>;
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(int_ppc_altivec_vprtybw v4i32:$vB))]>;
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def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", []>;
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def VPRTYBD : VX_VT5_EO5_VB5<1538, 9, "vprtybd", [(set v2i64:$vD,
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(int_ppc_altivec_vprtybd v2i64:$vB))]>;
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def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", [(set v1i128:$vD,
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(int_ppc_altivec_vprtybq v1i128:$vB))]>;
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// Vector (Bit) Permute (Right-indexed)
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// Vector (Bit) Permute (Right-indexed)
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def VBPERMD : VXForm_1<1484, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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def VBPERMD : VXForm_1<1484, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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@ -145,3 +145,58 @@ declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1)
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; Function Attrs: nounwind readnone
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; Function Attrs: nounwind readnone
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declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1)
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declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1)
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; Function Attrs: nounwind readnone
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define i32 @testVCLZLSBB(<16 x i8> %a) {
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entry:
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%0 = tail call i32 @llvm.ppc.altivec.vclzlsbb(<16 x i8> %a)
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ret i32 %0
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; CHECK-LABEL: testVCLZLSBB
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; CHECK: vclzlsbb 3, 2
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.ppc.altivec.vclzlsbb(<16 x i8>)
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; Function Attrs: nounwind readnone
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define i32 @testVCTZLSBB(<16 x i8> %a) {
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entry:
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%0 = tail call i32 @llvm.ppc.altivec.vctzlsbb(<16 x i8> %a)
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ret i32 %0
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; CHECK-LABEL: testVCTZLSBB
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; CHECK: vctzlsbb 3, 2
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.ppc.altivec.vctzlsbb(<16 x i8>)
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; Function Attrs: nounwind readnone
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define <4 x i32> @testVPRTYBW(<4 x i32> %a) {
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.altivec.vprtybw(<4 x i32> %a)
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ret <4 x i32> %0
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; CHECK-LABEL: testVPRTYBW
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; CHECK: vprtybw 2, 2
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}
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.ppc.altivec.vprtybw(<4 x i32>)
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; Function Attrs: nounwind readnone
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define <2 x i64> @testVPRTYBD(<2 x i64> %a) {
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entry:
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%0 = tail call <2 x i64> @llvm.ppc.altivec.vprtybd(<2 x i64> %a)
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ret <2 x i64> %0
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; CHECK-LABEL: testVPRTYBD
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; CHECK: vprtybd 2, 2
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}
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; Function Attrs: nounwind readnone
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declare <2 x i64> @llvm.ppc.altivec.vprtybd(<2 x i64>)
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; Function Attrs: nounwind readnone
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define <1 x i128> @testVPRTYBQ(<1 x i128> %a) {
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entry:
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%0 = tail call <1 x i128> @llvm.ppc.altivec.vprtybq(<1 x i128> %a)
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ret <1 x i128> %0
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; CHECK-LABEL: testVPRTYBQ
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; CHECK: vprtybq 2, 2
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}
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; Function Attrs: nounwind readnone
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declare <1 x i128> @llvm.ppc.altivec.vprtybq(<1 x i128>)
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