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fix division! again!! pattern isel, prepare to die.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25353 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duraid Madina
parent
99cf50937d
commit
0c81dc887c
@ -199,11 +199,13 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
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Chain = TmpF3.getValue(1);
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TmpF4 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2);
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Chain = TmpF4.getValue(1);
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} else {
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TmpF3 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
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Chain = TmpF3.getValue(1);
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TmpF4 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
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Chain = TmpF4.getValue(1);
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} else { // is unsigned
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if(isModulus) { /* unsigned integer divides do not need any fcvt.x*f* insns */
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TmpF3 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
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Chain = TmpF3.getValue(1);
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TmpF4 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
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Chain = TmpF4.getValue(1);
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}
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}
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} else { // this is an FP divide/remainder, so we 'leak' some temp
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@ -214,116 +216,110 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
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// we start by computing an approximate reciprocal (good to 9 bits?)
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// note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
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TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
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if(isFP)
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TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
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TmpF3, TmpF4);
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else
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TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
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TmpF3, TmpF4);
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TmpPR = TmpF5.getValue(1);
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Chain = TmpF5.getValue(2);
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if(!isModulus) { // if this is a divide, we worry about div-by-zero
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SDOperand bogusPR = CurDAG->getTargetNode(IA64::CMPEQ, MVT::i1,
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CurDAG->getRegister(IA64::r0, MVT::i64),
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CurDAG->getRegister(IA64::r0, MVT::i64));
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Chain = bogusPR.getValue(1);
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TmpPR2 = CurDAG->getTargetNode(IA64::TPCMPNE, MVT::i1, bogusPR,
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CurDAG->getRegister(IA64::r0, MVT::i64),
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CurDAG->getRegister(IA64::r0, MVT::i64), TmpPR);
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Chain = TmpPR2.getValue(1);
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}
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// we'll need copies of F0 and F1
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SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
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SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
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// now we apply newton's method, thrice! (FIXME: this is ~72 bits of
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// precision, don't need this much for f32/i32)
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TmpF6 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
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SDOperand minusB;
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if(isModulus) { // for remainders, it'll be handy to have
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// copies of -input_b
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minusB = CurDAG->getTargetNode(IA64::SUB, MVT::i64,
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CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2);
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Chain = minusB.getValue(1);
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}
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SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
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TmpE0 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
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TmpF4, TmpF5, F1, TmpPR);
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Chain = TmpF6.getValue(1);
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TmpF7 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpF3, TmpF5, F0, TmpPR);
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Chain = TmpF7.getValue(1);
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TmpF8 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpF6, TmpF6, F0, TmpPR);
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Chain = TmpF8.getValue(1);
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TmpF9 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpF6, TmpF7, TmpF7, TmpPR);
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Chain = TmpF9.getValue(1);
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TmpF10 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpF6, TmpF5, TmpF5, TmpPR);
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Chain = TmpF10.getValue(1);
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TmpF11 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpF8, TmpF9, TmpF9, TmpPR);
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Chain = TmpF11.getValue(1);
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TmpF12 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpF8, TmpF10, TmpF10, TmpPR);
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Chain = TmpF12.getValue(1);
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TmpF13 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
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TmpF4, TmpF11, TmpF3, TmpPR);
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Chain = TmpF13.getValue(1);
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Chain = TmpE0.getValue(1);
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TmpY1 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpF5, TmpE0, TmpF5, TmpPR);
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Chain = TmpY1.getValue(1);
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TmpE1 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpE0, TmpE0, F0, TmpPR);
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Chain = TmpE1.getValue(1);
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TmpY2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpY1, TmpE1, TmpY1, TmpPR);
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Chain = TmpY2.getValue(1);
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// FIXME: this is unfortunate :(
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// the story is that the dest reg of the fnma above and the fma below
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// (and therefore possibly the src of the fcvt.fx[u] as well) cannot
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// be the same register, or this code breaks if the first argument is
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// zero. (e.g. without this hack, 0%8 yields -64, not 0.)
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TmpF14 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpF13, TmpF12, TmpF11, TmpPR);
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Chain = TmpF14.getValue(1);
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if(isModulus) { // XXX: fragile! fixes _only_ mod, *breaks* div! !
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SDOperand bogus = CurDAG->getTargetNode(IA64::IUSE, MVT::Other, TmpF13); // hack :(
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Chain = bogus.getValue(0); // hmmm
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}
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if(isFP) { // if this is an FP divide, we finish up here and exit early
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if(isModulus)
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assert(0 && "Sorry, try another FORTRAN compiler.");
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SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
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TmpE2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpE1, TmpE1, F0, TmpPR);
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Chain = TmpE2.getValue(1);
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TmpY3 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpY2, TmpE2, TmpY2, TmpPR);
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Chain = TmpY3.getValue(1);
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TmpQ0 = CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
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Tmp1, TmpY3, F0, TmpPR);
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Chain = TmpQ0.getValue(1);
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TmpR0 = CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
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Tmp2, TmpQ0, Tmp1, TmpPR);
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Chain = TmpR0.getValue(1);
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if(!isFP) {
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// round to an integer
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if(isSigned) {
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TmpF15 = CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, MVT::i64, TmpF14);
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Chain = TmpF15.getValue(1);
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}
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else {
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TmpF15 = CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, MVT::i64, TmpF14);
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Chain = TmpF15.getValue(1);
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}
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} else {
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TmpF15 = TmpF14;
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// EXERCISE: can you see why TmpF15=TmpF14 does not work here, and
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// we really do need the above FMOV? ;)
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}
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if(!isModulus) {
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if(isFP) { // extra worrying about div-by-zero
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// we do a 'conditional fmov' (of the correct result, depending
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// on how the frcpa predicate turned out)
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SDOperand bogoResult = CurDAG->getTargetNode(IA64::PFMOV, MVT::f64,
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TmpF12, TmpPR2);
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Chain = bogoResult.getValue(1);
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Result = CurDAG->getTargetNode(IA64::CFMOV, MVT::f64, bogoResult,
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TmpF15, TmpPR);
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// we want Result to have the same target register as the frcpa, so
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// we two-address hack it. See the comment "for this to work..." on
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// page 48 of Intel application note #245415
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Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
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TmpY3, TmpR0, TmpQ0, TmpPR);
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Chain = Result.getValue(1);
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}
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else {
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Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpF15);
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Chain = Result.getValue(1);
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}
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} else { // this is a modulus
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if(!isFP) {
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// answer = q * (-b) + a
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SDOperand TmpI = CurDAG->getTargetNode(IA64::SUB, MVT::i64,
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CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2);
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Chain = TmpI.getValue(1);
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SDOperand TmpF = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, TmpI);
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Chain = TmpF.getValue(1);
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SDOperand ModulusResult = CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
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TmpF15, TmpF, TmpF1);
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Chain = ModulusResult.getValue(1);
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Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, ModulusResult);
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Chain = Result.getValue(1);
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} else { // FP modulus! The horror... the horror....
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assert(0 && "sorry, no FP modulus just yet!\n!\n");
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}
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}
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return Result; // XXX: early exit!
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} else { // this is *not* an FP divide, so there's a bit left to do:
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SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
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TmpQ2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpF3, TmpY2, F0, TmpPR);
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Chain = TmpQ2.getValue(1);
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TmpR2 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
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TmpF4, TmpQ2, TmpF3, TmpPR);
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Chain = TmpR2.getValue(1);
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return Result;
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// we want TmpQ3 to have the same target register as the frcpa, so
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// we two-address hack it. See the comment "for this to work..." on
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// page 48 of Intel application note #245415
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TmpQ3 = CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
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TmpR2, TmpR2, TmpY2, TmpQ2, TmpPR);
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Chain = TmpQ3.getValue(1);
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if(isSigned)
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TmpQ = CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, MVT::f64, TmpQ3);
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else
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TmpQ = CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, MVT::f64, TmpQ3);
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Chain = TmpQ.getValue(1);
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if(isModulus) {
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SDOperand FPminusB = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64,
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minusB);
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Chain = FPminusB.getValue(1);
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SDOperand Remainder = CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
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TmpQ, FPminusB, TmpF1);
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Chain = Remainder.getValue(1);
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Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
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Chain = Result.getValue(1);
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} else { // just an integer divide
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Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
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Chain = Result.getValue(1);
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}
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return Result;
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} // wasn't an FP divide
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}
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// Select - Convert the specified operand from a target-independent to a
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@ -589,6 +589,15 @@ def FNEGABS : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src),
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"fnegabs $dst = $src;;",
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[(set FP:$dst, (fneg (fabs FP:$src)))]>;
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let isTwoAddress=1 in {
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def TCFMAS1 : AForm<0x03, 0x0b,
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(ops FP:$dst, FP:$bogussrc, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
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"($qp) fma.s1 $dst = $src1, $src2, $src3;;">;
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def TCFMADS0 : AForm<0x03, 0x0b,
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(ops FP:$dst, FP:$bogussrc, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
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"($qp) fma.d.s0 $dst = $src1, $src2, $src3;;">;
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}
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def CFMAS1 : AForm<0x03, 0x0b,
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(ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
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"($qp) fma.s1 $dst = $src1, $src2, $src3;;">;
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@ -596,6 +605,18 @@ def CFNMAS1 : AForm<0x03, 0x0b,
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(ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
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"($qp) fnma.s1 $dst = $src1, $src2, $src3;;">;
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def CFMADS1 : AForm<0x03, 0x0b,
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(ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
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"($qp) fma.d.s1 $dst = $src1, $src2, $src3;;">;
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def CFMADS0 : AForm<0x03, 0x0b,
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(ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
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"($qp) fma.d.s0 $dst = $src1, $src2, $src3;;">;
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def CFNMADS1 : AForm<0x03, 0x0b,
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(ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
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"($qp) fnma.d.s1 $dst = $src1, $src2, $src3;;">;
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def FRCPAS0 : AForm<0x03, 0x0b, (ops FP:$dstFR, PR:$dstPR, FP:$src1, FP:$src2),
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"frcpa.s0 $dstFR, $dstPR = $src1, $src2;;">;
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def FRCPAS1 : AForm<0x03, 0x0b, (ops FP:$dstFR, PR:$dstPR, FP:$src1, FP:$src2),
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"frcpa.s1 $dstFR, $dstPR = $src1, $src2;;">;
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