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[ARM] Add a div regression test for Cortex-M23
Summary: This file was missed in the commit for Cortex-M23 and Cortex-M33 support. See https://reviews.llvm.org/D29073?id=85814 . Reviewers: rengolin, javed.absar, samparker Reviewed By: samparker Subscribers: llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D30162 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295655 91177308-0d34-0410-b5e6-96231b3b80d8
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test/CodeGen/ARM/thumb1-div.ll
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67
test/CodeGen/ARM/thumb1-div.ll
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; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-m23 -march=thumb | \
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; RUN: FileCheck %s -check-prefix=CHECK
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define i32 @f1(i32 %a, i32 %b) {
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entry:
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; CHECK-LABEL: f1
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; CHECK: sdiv
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%tmp1 = sdiv i32 %a, %b ; <i32> [#uses=1]
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ret i32 %tmp1
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}
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define i32 @f2(i32 %a, i32 %b) {
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entry:
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; CHECK-LABEL: f2
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; CHECK: udiv
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%tmp1 = udiv i32 %a, %b ; <i32> [#uses=1]
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ret i32 %tmp1
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}
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define i32 @f3(i32 %a, i32 %b) {
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entry:
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; CHECK-LABEL: f3
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%tmp1 = srem i32 %a, %b ; <i32> [#uses=1]
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ret i32 %tmp1
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; CHECK: sdiv
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; CHECK-NEXT: muls
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; CHECK-NEXT: subs
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}
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define i32 @f4(i32 %a, i32 %b) {
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entry:
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; CHECK-LABEL: f4
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; CHECK: udiv
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; CHECK-NEXT: muls
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; CHECK-NEXT: subs
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%tmp1 = urem i32 %a, %b ; <i32> [#uses=1]
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ret i32 %tmp1
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}
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define i64 @f5(i64 %a, i64 %b) {
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entry:
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; CHECK-LABEL: f5
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; EABI MODE = Remainder in R2-R3, quotient in R0-R1
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; CHECK: __aeabi_ldivmod
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: mov r1, r3
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%tmp1 = srem i64 %a, %b ; <i64> [#uses=1]
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ret i64 %tmp1
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}
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define i64 @f6(i64 %a, i64 %b) {
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entry:
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; CHECK-LABEL: f6
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; EABI MODE = Remainder in R2-R3, quotient in R0-R1
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; CHECK: __aeabi_uldivmod
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; CHECK: mov r0, r2
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; CHECK: mov r1, r3
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%tmp1 = urem i64 %a, %b ; <i64> [#uses=1]
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ret i64 %tmp1
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}
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