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implement the non-relocation forms of memory operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95368 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -50,6 +50,9 @@ public:
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Val >>= 8;
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}
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}
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void EmitDisplacementField(const MCOperand *RelocOp, int DispVal,
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int64_t Adj, bool IsPCRel, raw_ostream &OS) const;
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inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
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unsigned RM) {
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@ -62,6 +65,13 @@ public:
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EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), OS);
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}
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void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
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raw_ostream &OS) const {
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// SIB byte is in the same format as the ModRMByte...
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EmitByte(ModRMByte(SS, Index, Base), OS);
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}
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void EmitMemModRMByte(const MCInst &MI, unsigned Op,
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unsigned RegOpcodeField, intptr_t PCAdj,
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raw_ostream &OS) const;
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@ -85,6 +95,45 @@ static bool isDisp8(int Value) {
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return Value == (signed char)Value;
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}
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void X86MCCodeEmitter::
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EmitDisplacementField(const MCOperand *RelocOp, int DispVal,
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int64_t Adj, bool IsPCRel, raw_ostream &OS) const {
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// If this is a simple integer displacement that doesn't require a relocation,
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// emit it now.
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if (!RelocOp) {
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EmitConstant(DispVal, 4, OS);
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return;
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}
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assert(0 && "Reloc not handled yet");
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#if 0
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// Otherwise, this is something that requires a relocation. Emit it as such
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// now.
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unsigned RelocType = Is64BitMode ?
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(IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
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: (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
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if (RelocOp->isGlobal()) {
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// In 64-bit static small code model, we could potentially emit absolute.
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// But it's probably not beneficial. If the MCE supports using RIP directly
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// do it, otherwise fallback to absolute (this is determined by IsPCRel).
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// 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
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// 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
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bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM);
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emitGlobalAddress(RelocOp->getGlobal(), RelocType, RelocOp->getOffset(),
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Adj, Indirect);
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} else if (RelocOp->isSymbol()) {
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emitExternalSymbolAddress(RelocOp->getSymbolName(), RelocType);
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} else if (RelocOp->isCPI()) {
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emitConstPoolAddress(RelocOp->getIndex(), RelocType,
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RelocOp->getOffset(), Adj);
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} else {
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assert(RelocOp->isJTI() && "Unexpected machine operand!");
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emitJumpTableAddress(RelocOp->getIndex(), RelocType, Adj);
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}
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#endif
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}
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void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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unsigned RegOpcodeField,
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intptr_t PCAdj,
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@ -97,6 +146,7 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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if (Op3.isImm()) {
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DispVal = Op3.getImm();
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} else {
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assert(0 && "Unknown operand");
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#if 0
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if (Op3.isGlobal()) {
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DispForReloc = &Op3;
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@ -120,10 +170,13 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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}
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const MCOperand &Base = MI.getOperand(Op);
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//const MCOperand &Scale = MI.getOperand(Op+1);
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const MCOperand &Scale = MI.getOperand(Op+1);
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const MCOperand &IndexReg = MI.getOperand(Op+2);
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unsigned BaseReg = Base.getReg();
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// FIXME: Eliminate!
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bool IsPCRel = false;
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// Is a SIB byte needed?
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// If no BaseReg, issue a RIP relative instruction only if the MCE can
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// resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
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@ -134,9 +187,7 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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if (BaseReg == 0 || BaseReg == X86::RIP) { // Just a displacement?
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// Emit special case [disp32] encoding
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EmitByte(ModRMByte(0, RegOpcodeField, 5), OS);
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#if 0
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emitDisplacementField(DispForReloc, DispVal, PCAdj, true);
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#endif
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EmitDisplacementField(DispForReloc, DispVal, PCAdj, true, OS);
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} else {
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unsigned BaseRegNo = GetX86RegNum(Base);
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if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
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@ -149,71 +200,66 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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} else {
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// Emit the most general non-SIB encoding: [REG+disp32]
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EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), OS);
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#if 0
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emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
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#endif
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EmitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel, OS);
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}
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}
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} else { // We need a SIB byte, so start by outputting the ModR/M byte first
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assert(IndexReg.getReg() != X86::ESP &&
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IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
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bool ForceDisp32 = false;
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bool ForceDisp8 = false;
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if (BaseReg == 0) {
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// If there is no base register, we emit the special case SIB byte with
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// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
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EmitByte(ModRMByte(0, RegOpcodeField, 4), OS);
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ForceDisp32 = true;
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} else if (DispForReloc) {
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// Emit the normal disp32 encoding.
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EmitByte(ModRMByte(2, RegOpcodeField, 4), OS);
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ForceDisp32 = true;
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} else if (DispVal == 0 && BaseReg != X86::EBP) {
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// Emit no displacement ModR/M byte
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EmitByte(ModRMByte(0, RegOpcodeField, 4), OS);
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} else if (isDisp8(DispVal)) {
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// Emit the disp8 encoding.
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EmitByte(ModRMByte(1, RegOpcodeField, 4), OS);
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ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
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} else {
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// Emit the normal disp32 encoding.
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EmitByte(ModRMByte(2, RegOpcodeField, 4), OS);
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}
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#if 0
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// Calculate what the SS field value should be...
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static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
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unsigned SS = SSTable[Scale.getImm()];
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if (BaseReg == 0) {
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// Handle the SIB byte for the case where there is no base, see Intel
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// Manual 2A, table 2-7. The displacement has already been output.
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unsigned IndexRegNo;
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if (IndexReg.getReg())
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IndexRegNo = getX86RegNum(IndexReg.getReg());
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else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
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IndexRegNo = 4;
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emitSIBByte(SS, IndexRegNo, 5);
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} else {
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unsigned BaseRegNo = getX86RegNum(BaseReg);
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unsigned IndexRegNo;
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if (IndexReg.getReg())
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IndexRegNo = getX86RegNum(IndexReg.getReg());
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else
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IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
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emitSIBByte(SS, IndexRegNo, BaseRegNo);
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}
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// Do we need to output a displacement?
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if (ForceDisp8) {
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emitConstant(DispVal, 1);
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} else if (DispVal != 0 || ForceDisp32) {
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emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
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}
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#endif
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return;
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}
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// We need a SIB byte, so start by outputting the ModR/M byte first
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assert(IndexReg.getReg() != X86::ESP &&
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IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
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bool ForceDisp32 = false;
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bool ForceDisp8 = false;
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if (BaseReg == 0) {
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// If there is no base register, we emit the special case SIB byte with
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// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
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EmitByte(ModRMByte(0, RegOpcodeField, 4), OS);
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ForceDisp32 = true;
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} else if (DispForReloc) {
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// Emit the normal disp32 encoding.
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EmitByte(ModRMByte(2, RegOpcodeField, 4), OS);
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ForceDisp32 = true;
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} else if (DispVal == 0 && BaseReg != X86::EBP) {
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// Emit no displacement ModR/M byte
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EmitByte(ModRMByte(0, RegOpcodeField, 4), OS);
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} else if (isDisp8(DispVal)) {
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// Emit the disp8 encoding.
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EmitByte(ModRMByte(1, RegOpcodeField, 4), OS);
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ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
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} else {
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// Emit the normal disp32 encoding.
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EmitByte(ModRMByte(2, RegOpcodeField, 4), OS);
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}
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// Calculate what the SS field value should be...
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static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
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unsigned SS = SSTable[Scale.getImm()];
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if (BaseReg == 0) {
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// Handle the SIB byte for the case where there is no base, see Intel
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// Manual 2A, table 2-7. The displacement has already been output.
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unsigned IndexRegNo;
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if (IndexReg.getReg())
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IndexRegNo = GetX86RegNum(IndexReg);
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else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
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IndexRegNo = 4;
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EmitSIBByte(SS, IndexRegNo, 5, OS);
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} else {
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unsigned IndexRegNo;
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if (IndexReg.getReg())
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IndexRegNo = GetX86RegNum(IndexReg);
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else
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IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
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EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), OS);
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}
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// Do we need to output a displacement?
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if (ForceDisp8)
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EmitConstant(DispVal, 1, OS);
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else if (DispVal != 0 || ForceDisp32)
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EmitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel, OS);
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}
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