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[RDF] Switch RegisterAggr to a bit vector of register units
This avoids many complications related to the complex register aliasing schemes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300345 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek
parent
ec87df5c2d
commit
0e9e7d51d9
@ -259,7 +259,7 @@ void HexagonOptAddrMode::getAllRealUses(NodeAddr<StmtNode *> SA,
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<< Print<Liveness::RefMap>(phiUse, *DFG) << "\n");
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if (!phiUse.empty()) {
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for (auto I : phiUse) {
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if (DR.Reg != I.first)
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if (!DFG->getPRI().alias(RegisterRef(I.first), DR))
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continue;
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auto phiUseSet = I.second;
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for (auto phiUI : phiUseSet) {
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@ -913,10 +913,11 @@ void DataFlowGraph::build(unsigned Options) {
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}
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// Add function-entry phi nodes for the live-in registers.
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for (std::pair<RegisterId,LaneBitmask> P : LiveIns) {
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//for (std::pair<RegisterId,LaneBitmask> P : LiveIns) {
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for (auto I = LiveIns.rr_begin(), E = LiveIns.rr_end(); I != E; ++I) {
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RegisterRef RR = *I;
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NodeAddr<PhiNode*> PA = newPhi(EA);
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uint16_t PhiFlags = NodeAttrs::PhiRef | NodeAttrs::Preserving;
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RegisterRef RR(P.first, P.second);
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NodeAddr<DefNode*> DA = newDef(PA, RR, PhiFlags);
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PA.Addr->addMember(DA, *this);
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}
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@ -993,9 +994,9 @@ RegisterRef DataFlowGraph::restrictRef(RegisterRef AR, RegisterRef BR) const {
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return M.any() ? RegisterRef(AR.Reg, M) : RegisterRef();
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}
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#ifndef NDEBUG
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RegisterRef NAR = PRI.normalize(AR);
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RegisterRef NBR = PRI.normalize(BR);
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assert(NAR.Reg != NBR.Reg);
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// RegisterRef NAR = PRI.normalize(AR);
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// RegisterRef NBR = PRI.normalize(BR);
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// assert(NAR.Reg != NBR.Reg);
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#endif
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// This isn't strictly correct, because the overlap may happen in the
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// part masked out.
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@ -797,19 +797,9 @@ void Liveness::computeLiveIns() {
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//dbgs() << "\tcomp = " << Print<RegisterAggr>(LiveMap[&B], DFG) << '\n';
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LV.clear();
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for (std::pair<RegisterId,LaneBitmask> P : LiveMap[&B]) {
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MCSubRegIndexIterator S(P.first, &TRI);
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if (!S.isValid()) {
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LV.push_back(RegisterRef(P.first));
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continue;
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}
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do {
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LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());
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if ((M & P.second).any())
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LV.push_back(RegisterRef(S.getSubReg()));
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++S;
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} while (S.isValid());
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}
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const RegisterAggr &LG = LiveMap[&B];
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for (auto I = LG.rr_begin(), E = LG.rr_end(); I != E; ++I)
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LV.push_back(*I);
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std::sort(LV.begin(), LV.end());
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dbgs() << "\tcomp = {";
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for (auto I : LV)
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@ -830,9 +820,10 @@ void Liveness::resetLiveIns() {
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for (auto I : T)
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B.removeLiveIn(I);
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// Add the newly computed live-ins.
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auto &LiveIns = LiveMap[&B];
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for (auto I : LiveIns) {
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B.addLiveIn({MCPhysReg(I.first), I.second});
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const RegisterAggr &LiveIns = LiveMap[&B];
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for (auto I = LiveIns.rr_begin(), E = LiveIns.rr_end(); I != E; ++I) {
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RegisterRef R = *I;
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B.addLiveIn({MCPhysReg(R.Reg), R.Mask});
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}
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}
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}
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@ -1032,10 +1023,9 @@ void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) {
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// registers are not covering LRef. The first def from the
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// upward chain will be live.
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// Subtract all accumulated defs (RRs) from LRef.
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RegisterAggr L(PRI);
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L.insert(LRef).clear(RRs);
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assert(!L.empty());
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NewDefs.insert({TA.Id,L.begin()->second});
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RegisterRef T = RRs.clearIn(LRef);
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assert(T);
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NewDefs.insert({TA.Id,T.Mask});
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break;
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}
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@ -33,22 +33,33 @@ PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri,
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}
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}
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auto HasPartialOverlaps = [this] (uint32_t Reg) -> bool {
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for (MCRegAliasIterator A(Reg, &TRI, false); A.isValid(); ++A)
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if (!TRI.isSubRegister(Reg, *A) && !TRI.isSubRegister(*A, Reg))
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return true;
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return false;
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};
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UnitInfos.resize(TRI.getNumRegUnits());
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for (MCPhysReg R = 1, NR = TRI.getNumRegs(); R != NR; ++R)
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RegInfos[R].Partial = HasPartialOverlaps(R);
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for (MCPhysReg R = 1, NR = TRI.getNumRegs(); R != NR; ++R) {
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MCPhysReg SuperR = R;
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for (MCSuperRegIterator S(R, &TRI, false); S.isValid(); ++S)
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if (!RegInfos[*S].Partial)
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SuperR = *S;
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RegInfos[R].MaxSuper = SuperR;
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for (uint32_t U = 0, NU = TRI.getNumRegUnits(); U != NU; ++U) {
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if (UnitInfos[U].Reg != 0)
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continue;
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MCRegUnitRootIterator R(U, &TRI);
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assert(R.isValid());
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RegisterId F = *R;
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++R;
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if (R.isValid()) {
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UnitInfos[U].Mask = LaneBitmask::getAll();
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UnitInfos[U].Reg = F;
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} else {
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for (MCRegUnitMaskIterator I(F, &TRI); I.isValid(); ++I) {
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std::pair<uint32_t,LaneBitmask> P = *I;
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UnitInfo &UI = UnitInfos[P.first];
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UI.Reg = F;
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if (P.second.any()) {
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UI.Mask = P.second;
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} else {
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if (const TargetRegisterClass *RC = RegInfos[F].RegClass)
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UI.Mask = RC->LaneMask;
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else
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UI.Mask = LaneBitmask::getAll();
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}
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}
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}
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}
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for (const uint32_t *RM : TRI.getRegMasks())
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@ -61,22 +72,7 @@ PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri,
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}
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RegisterRef PhysicalRegisterInfo::normalize(RegisterRef RR) const {
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if (PhysicalRegisterInfo::isRegMaskId(RR.Reg))
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return RR;
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RegisterId SuperReg = RegInfos[RR.Reg].MaxSuper;
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if (RR.Reg == SuperReg)
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return RR;
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const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass;
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LaneBitmask RCMask = RC != nullptr ? RC->LaneMask : LaneBitmask(0x00000001);
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LaneBitmask Common = RR.Mask & RCMask;
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// Ex: IP/EIP/RIP
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// assert(RC != nullptr || RR.Reg == SuperReg);
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uint32_t Sub = TRI.getSubRegIndex(SuperReg, RR.Reg);
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LaneBitmask SuperMask = TRI.composeSubRegIndexLaneMask(Sub, Common);
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assert(RR.Mask.none() || SuperMask.any());
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return RegisterRef(SuperReg, SuperMask);
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return RR;
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}
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std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterId Reg) const {
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@ -217,19 +213,11 @@ bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
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return false;
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}
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RegisterRef NR = PRI.normalize(RR);
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auto F = Masks.find(NR.Reg);
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if (F != Masks.end()) {
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if ((F->second & NR.Mask).any())
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return true;
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}
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if (CheckUnits || PRI.hasPartialOverlaps(NR.Reg)) {
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for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
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std::pair<RegisterId,LaneBitmask> P = *U;
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if (P.second.none() || (P.second & RR.Mask).any())
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if (ExpUnits.test(P.first))
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return true;
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}
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for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
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std::pair<uint32_t,LaneBitmask> P = *U;
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if (P.second.none() || (P.second & RR.Mask).any())
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if (Units.test(P.first))
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return true;
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}
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return false;
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}
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@ -247,25 +235,13 @@ bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
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return true;
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}
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// Always have a cover for empty lane mask.
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RegisterRef NR = PRI.normalize(RR);
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if (NR.Mask.none())
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return true;
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auto F = Masks.find(NR.Reg);
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if (F != Masks.end()) {
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if ((NR.Mask & F->second) == NR.Mask)
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return true;
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for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
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std::pair<uint32_t,LaneBitmask> P = *U;
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if (P.second.none() || (P.second & RR.Mask).any())
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if (!Units.test(P.first))
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return false;
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}
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if (CheckUnits || PRI.hasPartialOverlaps(NR.Reg)) {
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for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
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std::pair<RegisterId,LaneBitmask> P = *U;
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if (P.second.none() || (P.second & RR.Mask).any())
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if (!ExpUnits.test(P.first))
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return false;
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}
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return true;
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}
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return false;
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return true;
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}
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RegisterAggr &RegisterAggr::insert(RegisterRef RR) {
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@ -280,99 +256,34 @@ RegisterAggr &RegisterAggr::insert(RegisterRef RR) {
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return *this;
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}
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RegisterRef NR = PRI.normalize(RR);
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auto F = Masks.find(NR.Reg);
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if (F == Masks.end())
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Masks.insert({NR.Reg, NR.Mask});
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else
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F->second |= NR.Mask;
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// If the register has any partial overlaps, the mask will not be sufficient
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// to accurately represent aliasing/covering information. Add all units to
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// the bit vector.
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if (PRI.hasPartialOverlaps(NR.Reg)) {
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for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
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std::pair<RegisterId,LaneBitmask> P = *U;
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if (P.second.none() || (P.second & RR.Mask).none())
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continue;
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ExpUnits.set(P.first);
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CheckUnits = true;
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}
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for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
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std::pair<uint32_t,LaneBitmask> P = *U;
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if (P.second.none() || (P.second & RR.Mask).any())
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Units.set(P.first);
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}
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return *this;
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}
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RegisterAggr &RegisterAggr::insert(const RegisterAggr &RG) {
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for (std::pair<RegisterId,LaneBitmask> P : RG.Masks)
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insert(RegisterRef(P.first, P.second));
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Units |= RG.Units;
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return *this;
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}
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RegisterAggr &RegisterAggr::intersect(RegisterRef RR) {
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if (PhysicalRegisterInfo::isRegMaskId(RR.Reg))
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return intersect(RegisterAggr(PRI).insert(RR));
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RegisterRef NR = PRI.normalize(RR);
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auto F = Masks.find(NR.Reg);
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LaneBitmask M;
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if (F != Masks.end())
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M = NR.Mask & F->second;
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Masks.clear();
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ExpUnits.clear();
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CheckUnits = false;
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if (M.any())
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insert(RegisterRef(NR.Reg, M));
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return *this;
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return intersect(RegisterAggr(PRI).insert(RR));
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}
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RegisterAggr &RegisterAggr::intersect(const RegisterAggr &RG) {
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for (auto I = Masks.begin(); I != Masks.end(); ) {
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auto F = RG.Masks.find(I->first);
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if (F == RG.Masks.end()) {
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I = Masks.erase(I);
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} else {
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I->second &= F->second;
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++I;
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}
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}
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if (CheckUnits && RG.CheckUnits) {
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ExpUnits &= RG.ExpUnits;
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if (ExpUnits.empty())
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CheckUnits = false;
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} else {
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ExpUnits.clear();
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CheckUnits = false;
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}
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Units &= RG.Units;
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return *this;
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}
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RegisterAggr &RegisterAggr::clear(RegisterRef RR) {
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if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) {
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// XXX SLOW
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const uint32_t *MB = PRI.getRegMaskBits(RR.Reg);
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for (unsigned i = 1, e = PRI.getTRI().getNumRegs(); i != e; ++i) {
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if (MB[i/32] & (1u << (i%32)))
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continue;
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clear(RegisterRef(i, LaneBitmask::getAll()));
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}
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return *this;
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}
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RegisterRef NR = PRI.normalize(RR);
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auto F = Masks.find(NR.Reg);
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if (F == Masks.end())
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return *this;
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LaneBitmask NewM = F->second & ~NR.Mask;
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if (NewM.none())
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Masks.erase(F);
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else
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F->second = NewM;
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return *this;
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return clear(RegisterAggr(PRI).insert(RR));
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}
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RegisterAggr &RegisterAggr::clear(const RegisterAggr &RG) {
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for (std::pair<RegisterId,LaneBitmask> P : RG.Masks)
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clear(RegisterRef(P.first, P.second));
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Units.reset(RG.Units);
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return *this;
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}
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@ -381,22 +292,75 @@ RegisterRef RegisterAggr::intersectWith(RegisterRef RR) const {
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T.insert(RR).intersect(*this);
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if (T.empty())
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return RegisterRef();
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return RegisterRef(T.begin()->first, T.begin()->second);
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RegisterRef NR = T.makeRegRef();
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assert(NR);
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return NR;
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}
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RegisterRef RegisterAggr::clearIn(RegisterRef RR) const {
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RegisterAggr T(PRI);
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T.insert(RR).clear(*this);
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if (T.empty())
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return RegisterAggr(PRI).insert(RR).clear(*this).makeRegRef();
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}
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RegisterRef RegisterAggr::makeRegRef() const {
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int U = Units.find_first();
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if (U < 0)
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return RegisterRef();
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return RegisterRef(T.begin()->first, T.begin()->second);
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auto AliasedRegs = [this] (uint32_t Unit, BitVector &Regs) {
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for (MCRegUnitRootIterator R(Unit, &PRI.getTRI()); R.isValid(); ++R)
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for (MCSuperRegIterator S(*R, &PRI.getTRI(), true); S.isValid(); ++S)
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Regs.set(*S);
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};
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// Find the set of all registers that are aliased to all the units
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// in this aggregate.
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// Get all the registers aliased to the first unit in the bit vector.
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BitVector Regs(PRI.getTRI().getNumRegs());
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AliasedRegs(U, Regs);
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U = Units.find_next(U);
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// For each other unit, intersect it with the set of all registers
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// aliased that unit.
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while (U >= 0) {
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BitVector AR(PRI.getTRI().getNumRegs());
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AliasedRegs(U, AR);
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Regs &= AR;
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U = Units.find_next(U);
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}
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// If there is at least one register remaining, pick the first one,
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// and consolidate the masks of all of its units contained in this
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// aggregate.
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int F = Regs.find_first();
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if (F <= 0)
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return RegisterRef();
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LaneBitmask M;
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for (MCRegUnitMaskIterator I(F, &PRI.getTRI()); I.isValid(); ++I) {
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std::pair<uint32_t,LaneBitmask> P = *I;
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if (Units.test(P.first))
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M |= P.second.none() ? LaneBitmask::getAll() : P.second;
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}
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return RegisterRef(F, M);
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}
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void RegisterAggr::print(raw_ostream &OS) const {
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OS << '{';
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for (auto I : Masks)
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OS << ' ' << PrintReg(I.first, &PRI.getTRI())
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<< PrintLaneMaskOpt(I.second);
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for (int U = Units.find_first(); U >= 0; U = Units.find_next(U))
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OS << ' ' << PrintRegUnit(U, &PRI.getTRI());
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OS << " }";
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}
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RegisterAggr::rr_iterator::rr_iterator(const RegisterAggr &RG,
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bool End)
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: Owner(&RG) {
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for (int U = RG.Units.find_first(); U >= 0; U = RG.Units.find_next(U)) {
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RegisterRef R = RG.PRI.getRefForUnit(U);
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Masks[R.Reg] |= R.Mask;
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}
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Pos = End ? Masks.end() : Masks.begin();
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Index = End ? Masks.size() : 0;
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}
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@ -103,21 +103,25 @@ namespace rdf {
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return !isRegMaskId(RB.Reg) ? aliasRM(RB, RA) : aliasMM(RA, RB);
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}
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std::set<RegisterId> getAliasSet(RegisterId Reg) const;
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bool hasPartialOverlaps(RegisterId Reg) const {
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return RegInfos[Reg].Partial;
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RegisterRef getRefForUnit(uint32_t U) const {
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return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask);
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}
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const TargetRegisterInfo &getTRI() const { return TRI; }
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||||
private:
|
||||
struct RegInfo {
|
||||
unsigned MaxSuper = 0;
|
||||
const TargetRegisterClass *RegClass = nullptr;
|
||||
bool Partial = false;
|
||||
};
|
||||
struct UnitInfo {
|
||||
RegisterId Reg = 0;
|
||||
LaneBitmask Mask;
|
||||
};
|
||||
|
||||
const TargetRegisterInfo &TRI;
|
||||
std::vector<RegInfo> RegInfos;
|
||||
std::vector<UnitInfo> UnitInfos;
|
||||
IndexedSet<const uint32_t*> RegMasks;
|
||||
|
||||
bool aliasRR(RegisterRef RA, RegisterRef RB) const;
|
||||
@ -128,10 +132,10 @@ namespace rdf {
|
||||
|
||||
struct RegisterAggr {
|
||||
RegisterAggr(const PhysicalRegisterInfo &pri)
|
||||
: ExpUnits(pri.getTRI().getNumRegUnits()), PRI(pri) {}
|
||||
: Units(pri.getTRI().getNumRegUnits()), PRI(pri) {}
|
||||
RegisterAggr(const RegisterAggr &RG) = default;
|
||||
|
||||
bool empty() const { return Masks.empty(); }
|
||||
bool empty() const { return Units.empty(); }
|
||||
bool hasAliasOf(RegisterRef RR) const;
|
||||
bool hasCoverOf(RegisterRef RR) const;
|
||||
static bool isCoverOf(RegisterRef RA, RegisterRef RB,
|
||||
@ -148,21 +152,45 @@ namespace rdf {
|
||||
|
||||
RegisterRef intersectWith(RegisterRef RR) const;
|
||||
RegisterRef clearIn(RegisterRef RR) const;
|
||||
RegisterRef makeRegRef() const;
|
||||
|
||||
void print(raw_ostream &OS) const;
|
||||
|
||||
private:
|
||||
typedef std::unordered_map<RegisterId, LaneBitmask> MapType;
|
||||
struct rr_iterator {
|
||||
typedef std::map<RegisterId,LaneBitmask> MapType;
|
||||
private:
|
||||
MapType Masks;
|
||||
MapType::iterator Pos;
|
||||
unsigned Index;
|
||||
const RegisterAggr *Owner;
|
||||
public:
|
||||
rr_iterator(const RegisterAggr &RG, bool End);
|
||||
RegisterRef operator*() const {
|
||||
return RegisterRef(Pos->first, Pos->second);
|
||||
}
|
||||
rr_iterator &operator++() {
|
||||
++Pos;
|
||||
++Index;
|
||||
return *this;
|
||||
}
|
||||
bool operator==(const rr_iterator &I) const {
|
||||
assert(Owner == I.Owner);
|
||||
return Index == I.Index;
|
||||
}
|
||||
bool operator!=(const rr_iterator &I) const {
|
||||
return !(*this == I);
|
||||
}
|
||||
};
|
||||
|
||||
public:
|
||||
typedef MapType::const_iterator iterator;
|
||||
iterator begin() const { return Masks.begin(); }
|
||||
iterator end() const { return Masks.end(); }
|
||||
rr_iterator rr_begin() const {
|
||||
return rr_iterator(*this, false);
|
||||
}
|
||||
rr_iterator rr_end() const {
|
||||
return rr_iterator(*this, true);
|
||||
}
|
||||
|
||||
private:
|
||||
MapType Masks;
|
||||
BitVector ExpUnits; // Register units for explicit checks.
|
||||
bool CheckUnits = false;
|
||||
BitVector Units;
|
||||
const PhysicalRegisterInfo &PRI;
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user