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move a bunch of register constraints from being handled by
getRegClassForInlineAsmConstraint to being handled by getRegForInlineAsmConstraint. This allows us to let the llvm register allocator allocate, which gives us better code. For example, X86/2007-01-29-InlineAsm-ir.ll used to compile to: _run_init_process: subl $4, %esp movl %ebx, (%esp) xorl %ebx, %ebx movl $11, %eax movl %ebx, %ecx movl %ebx, %edx # InlineAsm Start push %ebx ; movl %ebx,%ebx ; int $0x80 ; pop %ebx # InlineAsm End Now we get: _run_init_process: xorl %ecx, %ecx movl $11, %eax movl %ecx, %edx # InlineAsm Start push %ebx ; movl %ecx,%ebx ; int $0x80 ; pop %ebx # InlineAsm End git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35804 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4645,39 +4645,12 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
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MVT::ValueType VT) const {
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if (Constraint.size() == 1) {
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// FIXME: not handling fp-stack yet!
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// FIXME: not handling MMX registers yet ('y' constraint).
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switch (Constraint[0]) { // GCC X86 Constraint Letters
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default: break; // Unknown constraint letter
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case 'A': // EAX/EDX
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if (VT == MVT::i32 || VT == MVT::i64)
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return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
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break;
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case 'r': // GENERAL_REGS
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case 'R': // LEGACY_REGS
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if (VT == MVT::i64 && Subtarget->is64Bit())
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return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
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X86::RSI, X86::RDI, X86::RBP, X86::RSP,
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X86::R8, X86::R9, X86::R10, X86::R11,
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X86::R12, X86::R13, X86::R14, X86::R15, 0);
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if (VT == MVT::i32)
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return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
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X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0);
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else if (VT == MVT::i16)
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return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
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X86::SI, X86::DI, X86::BP, X86::SP, 0);
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else if (VT == MVT::i8)
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return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
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break;
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case 'l': // INDEX_REGS
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if (VT == MVT::i32)
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return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
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X86::ESI, X86::EDI, X86::EBP, 0);
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else if (VT == MVT::i16)
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return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
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X86::SI, X86::DI, X86::BP, 0);
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else if (VT == MVT::i8)
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return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
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break;
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case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
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case 'Q': // Q_REGS
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if (VT == MVT::i32)
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@ -4687,18 +4660,6 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
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else if (VT == MVT::i8)
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return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
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break;
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case 'x': // SSE_REGS if SSE1 allowed
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if (Subtarget->hasSSE1())
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return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
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X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
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0);
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return std::vector<unsigned>();
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case 'Y': // SSE_REGS if SSE2 allowed
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if (Subtarget->hasSSE2())
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return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
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X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
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0);
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return std::vector<unsigned>();
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}
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}
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@ -4714,11 +4675,44 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
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// GCC Constraint Letters
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switch (Constraint[0]) {
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default: break;
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case 'x':
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if (VT == MVT::f32 || VT == MVT::i32)
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case 'r': // GENERAL_REGS
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case 'R': // LEGACY_REGS
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case 'l': // INDEX_REGS
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if (VT == MVT::i64 && Subtarget->is64Bit())
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return std::make_pair(0U, X86::GR64RegisterClass);
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if (VT == MVT::i32)
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return std::make_pair(0U, X86::GR32RegisterClass);
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else if (VT == MVT::i16)
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return std::make_pair(0U, X86::GR16RegisterClass);
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else if (VT == MVT::i8)
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return std::make_pair(0U, X86::GR8RegisterClass);
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break;
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// FIXME: not handling MMX registers yet ('y' constraint).
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case 'Y': // SSE_REGS if SSE2 allowed
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if (!Subtarget->hasSSE2()) break;
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// FALL THROUGH.
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case 'x': // SSE_REGS if SSE1 allowed
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if (!Subtarget->hasSSE1()) break;
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switch (VT) {
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default: break;
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// Scalar SSE types.
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case MVT::f32:
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case MVT::i32:
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return std::make_pair(0U, X86::FR32RegisterClass);
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if (VT == MVT::f64 || VT == MVT::i64)
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case MVT::f64:
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case MVT::i64:
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return std::make_pair(0U, X86::FR64RegisterClass);
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// Vector types.
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case MVT::Vector:
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case MVT::v16i8:
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case MVT::v8i16:
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case MVT::v4i32:
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case MVT::v2i64:
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case MVT::v4f32:
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case MVT::v2f64:
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return std::make_pair(0U, X86::VR128RegisterClass);
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}
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break;
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}
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}
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