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Change addTypeForNeon to use MVT instead of EVT so all the calls to getSimpleVT can be removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161735 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -90,75 +90,70 @@ static const uint16_t GPRArgRegs[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3
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};
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void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
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EVT PromotedBitwiseVT) {
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void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
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MVT PromotedBitwiseVT) {
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if (VT != PromotedLdStVT) {
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setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
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AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
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PromotedLdStVT.getSimpleVT());
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setOperationAction(ISD::LOAD, VT, Promote);
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AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
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setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
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AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
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PromotedLdStVT.getSimpleVT());
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setOperationAction(ISD::STORE, VT, Promote);
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AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
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}
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EVT ElemTy = VT.getVectorElementType();
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MVT ElemTy = VT.getVectorElementType();
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if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
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setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::SETCC, VT, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
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if (ElemTy == MVT::i32) {
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setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::SINT_TO_FP, VT, Custom);
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setOperationAction(ISD::UINT_TO_FP, VT, Custom);
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setOperationAction(ISD::FP_TO_SINT, VT, Custom);
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setOperationAction(ISD::FP_TO_UINT, VT, Custom);
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} else {
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setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
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setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
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setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
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setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
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setOperationAction(ISD::SINT_TO_FP, VT, Expand);
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setOperationAction(ISD::UINT_TO_FP, VT, Expand);
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setOperationAction(ISD::FP_TO_SINT, VT, Expand);
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setOperationAction(ISD::FP_TO_UINT, VT, Expand);
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}
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setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
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setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
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setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, VT.getSimpleVT(), Expand);
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setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
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setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
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setOperationAction(ISD::SELECT, VT, Expand);
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setOperationAction(ISD::SELECT_CC, VT, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
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if (VT.isInteger()) {
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setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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setOperationAction(ISD::SRL, VT, Custom);
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}
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// Promote all bit-wise operations.
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if (VT.isInteger() && VT != PromotedBitwiseVT) {
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setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
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AddPromotedToType (ISD::AND, VT.getSimpleVT(),
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PromotedBitwiseVT.getSimpleVT());
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setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
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AddPromotedToType (ISD::OR, VT.getSimpleVT(),
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PromotedBitwiseVT.getSimpleVT());
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setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
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AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
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PromotedBitwiseVT.getSimpleVT());
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setOperationAction(ISD::AND, VT, Promote);
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AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
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setOperationAction(ISD::OR, VT, Promote);
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AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
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setOperationAction(ISD::XOR, VT, Promote);
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AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
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}
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// Neon does not support vector divide/remainder operations.
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setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
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setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
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setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
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setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
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setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
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setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
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setOperationAction(ISD::SDIV, VT, Expand);
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setOperationAction(ISD::UDIV, VT, Expand);
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setOperationAction(ISD::FDIV, VT, Expand);
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setOperationAction(ISD::SREM, VT, Expand);
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setOperationAction(ISD::UREM, VT, Expand);
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setOperationAction(ISD::FREM, VT, Expand);
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}
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void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
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void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
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addRegisterClass(VT, &ARM::DPRRegClass);
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addTypeForNEON(VT, MVT::f64, MVT::v2i32);
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}
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void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
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void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
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addRegisterClass(VT, &ARM::QPRRegClass);
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addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
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}
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@ -397,9 +397,9 @@ namespace llvm {
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///
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unsigned ARMPCLabelIndex;
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void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
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void addDRTypeForNEON(EVT VT);
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void addQRTypeForNEON(EVT VT);
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void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
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void addDRTypeForNEON(MVT VT);
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void addQRTypeForNEON(MVT VT);
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typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
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void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
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