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ARM STRBT assembly parsing and encoding.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-08-11 20:04:56 +00:00
parent 961afdf1b6
commit 10348e70d5
3 changed files with 52 additions and 26 deletions
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60
lib/Target/ARM/ARMInstrInfo.td
View File

@ -2350,6 +2350,42 @@ def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
// STRT, STRBT, and STRHT
def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
IndexModePost, StFrm, IIC_iStore_bh_ru,
"strbt", "\t$Rt, $addr, $offset",
"$addr.base = $Rn_wb", []> {
// {12} isAdd
// {11-0} imm12/Rm
bits<14> offset;
bits<4> addr;
let Inst{25} = 1;
let Inst{23} = offset{12};
let Inst{21} = 1; // overwrite
let Inst{19-16} = addr;
let Inst{11-5} = offset{11-5};
let Inst{4} = 0;
let Inst{3-0} = offset{3-0};
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
IndexModePost, StFrm, IIC_iStore_bh_ru,
"strbt", "\t$Rt, $addr, $offset",
"$addr.base = $Rn_wb", []> {
// {12} isAdd
// {11-0} imm12/Rm
bits<14> offset;
bits<4> addr;
let Inst{25} = 0;
let Inst{23} = offset{12};
let Inst{21} = 1; // overwrite
let Inst{19-16} = addr;
let Inst{11-0} = offset{11-0};
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
def STRTr : AI2stridxT<0, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, ldst_so_reg:$addr),
IndexModePost, StFrm, IIC_iStore_ru,
@ -2373,30 +2409,6 @@ def STRTi : AI2stridxT<0, 0, (outs GPR:$Rn_wb),
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
def STRBTr : AI2stridxT<1, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, ldst_so_reg:$addr),
IndexModePost, StFrm, IIC_iStore_bh_ru,
"strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
[/* For disassembly only; pattern left blank */]> {
let Inst{25} = 1;
let Inst{21} = 1; // overwrite
let Inst{4} = 0;
let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
def STRBTi : AI2stridxT<1, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, addrmode_imm12:$addr),
IndexModePost, StFrm, IIC_iStore_bh_ru,
"strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
[/* For disassembly only; pattern left blank */]> {
let Inst{25} = 0;
let Inst{21} = 1; // overwrite
let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
multiclass AI3strT<bits<4> op, string opc> {
def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
(ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),

4
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -939,8 +939,8 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
case ARM::STR_POST_REG:
case ARM::STRTr:
case ARM::STRTi:
case ARM::STRBTr:
case ARM::STRBTi:
case ARM::STRBT_POST_REG:
case ARM::STRBT_POST_IMM:
if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
break;
default:

14
test/MC/ARM/arm-memory-instructions.s
View File

@ -375,3 +375,17 @@ _func:
@ CHECK: strb r7, [r12, -r3, lsl #5] @ encoding: [0x83,0x72,0x4c,0xe7]
@ CHECK: strb sp, [r7], r2, asr #12 @ encoding: [0x42,0xd6,0xc7,0xe6]
@------------------------------------------------------------------------------
@ STRBT
@------------------------------------------------------------------------------
@ FIXME: Optional offset operand.
strbt r6, [r2], #12
strbt r5, [r6], #-13
strbt r4, [r9], r5
strbt r3, [r8], -r2, lsl #3
@ CHECK: strbt r6, [r2], #12 @ encoding: [0x0c,0x60,0xe2,0xe4]
@ CHECK: strbt r5, [r6], #-13 @ encoding: [0x0d,0x50,0x66,0xe4]
@ CHECK: strbt r4, [r9], r5 @ encoding: [0x05,0x40,0xe9,0xe6]
@ CHECK: strbt r3, [r8], -r2, lsl #3 @ encoding: [0x82,0x31,0x68,0xe6]