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ARM assembly parsing for VST1 two-register encoding.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144430 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-11-11 23:45:47 +00:00
parent c7352f8ca0
commit 10a630dea6
1 changed files with 3 additions and 4 deletions
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7
lib/Target/ARM/ARMInstrNEON.td
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@ -1238,12 +1238,11 @@ class VST1D<bits<4> op7_4, string Dt>
let DecoderMethod = "DecodeVSTInstruction";
}
class VST1Q<bits<4> op7_4, string Dt>
: NLdSt<0,0b00,0b1010,op7_4, (outs),
(ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
"vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
: NLdSt<0,0b00,0b1010,op7_4, (outs), (ins VecListTwoD:$Vd, addrmode6:$Rn),
IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
let Rm = 0b1111;
let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVSTInstruction";
let DecoderMethod = "DecodeVLDInstruction";
}
def VST1d8 : VST1D<{0,0,0,?}, "8">;