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Bug 13662: Enable GPRPair for all i64 operands of inline asm on ARM
This patch assigns paired GPRs for inline asm with 64-bit data on ARM. It's enabled for both ARM and Thumb to support modifiers like %H, %Q, %R. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185169 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Weiming Zhao
parent
0ee20c9d80
commit
10ddc4d7f2
@ -464,8 +464,14 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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// This takes advantage of the 2 operand-ness of ldm/stm and that we've
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// already got the operands in registers that are operands to the
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// inline asm statement.
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O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
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O << "{";
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if (ARM::GPRPairRegClass.contains(RegBegin)) {
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const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
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unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
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O << ARMInstPrinter::getRegisterName(Reg0) << ", ";;
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RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
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}
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O << ARMInstPrinter::getRegisterName(RegBegin);
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// FIXME: The register allocator not only may not have given us the
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// registers in sequence, but may not be in ascending registers. This
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@ -491,6 +497,20 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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return true;
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unsigned Flags = FlagsOP.getImm();
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unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
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unsigned RC;
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InlineAsm::hasRegClassConstraint(Flags, RC);
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if (RC == ARM::GPRPairRegClassID) {
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if (NumVals != 1)
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return true;
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const MachineOperand &MO = MI->getOperand(OpNum);
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if (!MO.isReg())
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return true;
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const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
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unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
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ARM::gsub_0 : ARM::gsub_1);
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O << ARMInstPrinter::getRegisterName(Reg);
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return false;
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}
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if (NumVals != 2)
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return true;
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unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
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@ -3472,16 +3472,16 @@ SDNode *ARMDAGToDAGISel::SelectInlineAsm(SDNode *N){
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// However, some instrstions (e.g. ldrexd/strexd in ARM mode) require
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// (even/even+1) GPRs and use %n and %Hn to refer to the individual regs
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// respectively. Since there is no constraint to explicitly specify a
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// reg pair, we search %H operand inside the asm string. If it is found, the
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// transformation below enforces a GPRPair reg class for "%r" for 64-bit data.
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if (AsmString.find(":H}") == StringRef::npos)
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return NULL;
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// reg pair, we use GPRPair reg class for "%r" for 64-bit data. For Thumb,
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// the 64-bit data may be referred by H, Q, R modifiers, so we still pack
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// them into a GPRPair.
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SDLoc dl(N);
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SDValue Glue = N->getOperand(NumOps-1);
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SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps-1) : SDValue(0,0);
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SmallVector<bool, 8> OpChanged;
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// Glue node will be appended late.
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for(unsigned i = 0; i < NumOps -1; ++i) {
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for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
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SDValue op = N->getOperand(i);
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AsmNodeOperands.push_back(op);
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@ -3495,17 +3495,28 @@ SDNode *ARMDAGToDAGISel::SelectInlineAsm(SDNode *N){
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else
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continue;
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unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
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if (NumRegs)
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OpChanged.push_back(false);
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unsigned DefIdx = 0;
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bool IsTiedToChangedOp = false;
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// If it's a use that is tied with a previous def, it has no
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// reg class constraint.
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if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
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IsTiedToChangedOp = OpChanged[DefIdx];
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if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
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&& Kind != InlineAsm::Kind_RegDefEarlyClobber)
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continue;
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unsigned RegNum = InlineAsm::getNumOperandRegisters(Flag);
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unsigned RC;
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bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
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if (!HasRC || RC != ARM::GPRRegClassID || RegNum != 2)
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if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID))
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|| NumRegs != 2)
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continue;
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assert((i+2 < NumOps-1) && "Invalid number of operands in inline asm");
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assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
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SDValue V0 = N->getOperand(i+1);
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SDValue V1 = N->getOperand(i+2);
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unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
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@ -3566,6 +3577,7 @@ SDNode *ARMDAGToDAGISel::SelectInlineAsm(SDNode *N){
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Changed = true;
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if(PairedReg.getNode()) {
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OpChanged[OpChanged.size() -1 ] = true;
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Flag = InlineAsm::getFlagWord(Kind, 1 /* RegNum*/);
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Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID);
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// Replace the current flag.
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@ -3578,7 +3590,8 @@ SDNode *ARMDAGToDAGISel::SelectInlineAsm(SDNode *N){
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}
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}
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AsmNodeOperands.push_back(Glue);
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if (Glue.getNode())
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AsmNodeOperands.push_back(Glue);
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if (!Changed)
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return NULL;
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@ -1,5 +1,5 @@
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; RUN: llc < %s -O3 -mtriple=arm-linux-gnueabi | FileCheck %s
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; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s
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; check if regs are passing correctly
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define void @i64_write(i64* %p, i64 %val) nounwind {
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; CHECK: i64_write:
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@ -45,10 +45,43 @@ entry:
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; check if callee-saved registers used by inline asm are saved/restored
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define void @foo(i64* %p, i64 %i) nounwind {
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; CHECK:foo:
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; CHECK: push {{{r[4-9]|r10|r11}}
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; CHECK: {{push|push.w}} {{{r[4-9]|r10|r11}}
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
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; CHECK: pop {{{r[4-9]|r10|r11}}
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; CHECK: {{pop|pop.w}} {{{r[4-9]|r10|r11}}
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%1 = tail call { i64, i64 } asm sideeffect "@ atomic64_set\0A1: ldrexd $0, ${0:H}, [$3]\0Aldrexd $1, ${1:H}, [$3]\0A strexd $0, $4, ${4:H}, [$3]\0A teq $0, #0\0A bne 1b", "=&r,=&r,=*Qo,r,r,~{cc}"(i64* %p, i64* %p, i64 %i) nounwind
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ret void
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}
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; return *p;
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define i64 @ldrd_test(i64* %p) nounwind {
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; CHECK: ldrd_test:
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%1 = tail call i64 asm "ldrd $0, ${0:H}, [$1]", "=r,r"(i64* %p) nounwind
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ret i64 %1
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}
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define i64 @QR_test(i64* %p) nounwind {
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; CHECK: QR_test:
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; CHECK: ldrd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
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%1 = tail call i64 asm "ldrd ${0:Q}, ${0:R}, [$1]", "=r,r"(i64* %p) nounwind
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ret i64 %1
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}
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define i64 @defuse_test(i64 %p) nounwind {
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; CHECK: defuse_test:
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; CHECK: add {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, #1
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%1 = tail call i64 asm "add $0, ${0:H}, #1", "=r,0"(i64 %p) nounwind
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ret i64 %1
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}
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; *p = (hi << 32) | lo;
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define void @strd_test(i64* %p, i32 %lo, i32 %hi) nounwind {
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; CHECK: strd_test:
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; CHECK: strd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
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%1 = zext i32 %hi to i64
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%2 = shl nuw i64 %1, 32
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%3 = sext i32 %lo to i64
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%4 = or i64 %2, %3
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tail call void asm sideeffect "strd $0, ${0:H}, [$1]", "r,r"(i64 %4, i64* %p) nounwind
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ret void
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}
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