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Canonicalize splats as build_vectors (PR22283)

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This is a follow-on patch to:
http://reviews.llvm.org/D7093

That patch canonicalized constant splats as build_vectors, 
and this patch removes the constant check so we can canonicalize
all splats as build_vectors.

This fixes the 2nd test case in PR22283:
http://llvm.org/bugs/show_bug.cgi?id=22283

The unfortunate code duplication between SelectionDAG and DAGCombiner
is discussed in the earlier patch review. At least this patch is just
removing code...

This improves an existing x86 AVX test and changes codegen in an ARM test.

Differential Revision: http://reviews.llvm.org/D7389


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229511 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel 2015-02-17 16:54:32 +00:00
parent 7a7153e5ee
commit 1115b2c27e
4 changed files with 23 additions and 30 deletions
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21
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -11749,20 +11749,17 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
if (AllSame)
return N0;
// If the splatted element is a constant, just build the vector out of
// constants directly.
// Canonicalize any other splat as a build_vector.
const SDValue &Splatted = V->getOperand(SVN->getSplatIndex());
if (isa<ConstantSDNode>(Splatted) || isa<ConstantFPSDNode>(Splatted)) {
SmallVector<SDValue, 8> Ops(NumElts, Splatted);
SDValue NewBV = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
V->getValueType(0), Ops);
SmallVector<SDValue, 8> Ops(NumElts, Splatted);
SDValue NewBV = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
V->getValueType(0), Ops);
// We may have jumped through bitcasts, so the type of the
// BUILD_VECTOR may not match the type of the shuffle.
if (V->getValueType(0) != VT)
NewBV = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, NewBV);
return NewBV;
}
// We may have jumped through bitcasts, so the type of the
// BUILD_VECTOR may not match the type of the shuffle.
if (V->getValueType(0) != VT)
NewBV = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, NewBV);
return NewBV;
}
}

23
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1581,22 +1581,19 @@ SDValue SelectionDAG::getVectorShuffle(EVT VT, SDLoc dl, SDValue N1,
return N1;
}
// If the shuffle itself creates a constant splat, build the vector
// directly.
// If the shuffle itself creates a splat, build the vector directly.
if (AllSame && SameNumElts) {
const SDValue &Splatted = BV->getOperand(MaskVec[0]);
if (isa<ConstantSDNode>(Splatted) || isa<ConstantFPSDNode>(Splatted)) {
SmallVector<SDValue, 8> Ops(NElts, Splatted);
const SDValue &Splatted = BV->getOperand(MaskVec[0]);
SmallVector<SDValue, 8> Ops(NElts, Splatted);
SDValue NewBV =
getNode(ISD::BUILD_VECTOR, dl, BV->getValueType(0), Ops);
EVT BuildVT = BV->getValueType(0);
SDValue NewBV = getNode(ISD::BUILD_VECTOR, dl, BuildVT, Ops);
// We may have jumped through bitcasts, so the type of the
// BUILD_VECTOR may not match the type of the shuffle.
if (BV->getValueType(0) != VT)
NewBV = getNode(ISD::BITCAST, dl, VT, NewBV);
return NewBV;
}
// We may have jumped through bitcasts, so the type of the
// BUILD_VECTOR may not match the type of the shuffle.
if (BuildVT != VT)
NewBV = getNode(ISD::BITCAST, dl, VT, NewBV);
return NewBV;
}
}
}

6
test/CodeGen/ARM/vdup.ll
View File

@ -347,17 +347,17 @@ define <2 x float> @check_spr_splat2(<2 x float> %p, i16 %q) {
define <4 x float> @check_spr_splat4(<4 x float> %p, i16 %q) {
;CHECK-LABEL: check_spr_splat4:
;CHECK: vdup.32 q
;CHECK: vld1.16
%conv = sitofp i16 %q to float
%splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 0
%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
%sub = fsub <4 x float> %splat.splat, %p
ret <4 x float> %sub
}
; Same codegen as above test; scalar is splatted using vld1, so shuffle index is irrelevant.
define <4 x float> @check_spr_splat4_lane1(<4 x float> %p, i16 %q) {
;CHECK-LABEL: check_spr_splat4_lane1:
;CHECK: vdup.32 q{{.*}}, d{{.*}}[1]
;CHECK: vld1.16
%conv = sitofp i16 %q to float
%splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 1
%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>

3
test/CodeGen/X86/vector-shuffle-256-v4.ll
View File

@ -885,8 +885,7 @@ define <4 x double> @splat_mem_v4f64(double* %ptr) {
define <4 x i64> @splat_mem_v4i64(i64* %ptr) {
; AVX1-LABEL: splat_mem_v4i64:
; AVX1: # BB#0:
; AVX1-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vbroadcastsd (%rdi), %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: splat_mem_v4i64: