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Reapply r54147 with a constraint to only use the 8-bit
subreg form on x86-64, to avoid the problem with x86-32 having GPRs that don't have 8-bit subregs. Also, change several 16-bit instructions to use equivalent 32-bit instructions. These have a smaller encoding and avoid partial-register updates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54223 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
parent
912923925f
commit
11ba3b1af6
@ -241,18 +241,22 @@ def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
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"movs{lq|xd}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
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def MOVZX64rr8 : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
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"movz{bq|x}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (zext GR8:$src))]>, TB;
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def MOVZX64rm8 : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
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"movz{bq|x}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
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def MOVZX64rr16: RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
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"movz{wq|x}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (zext GR16:$src))]>, TB;
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def MOVZX64rm16: RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
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"movz{wq|x}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
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// Use movzbl instead of movzbq when the destination is a register; it's
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// equivalent due to implicit zero-extending, and it has a smaller encoding.
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def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
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"movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
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[(set GR64:$dst, (zext GR8:$src))]>, TB;
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def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
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"movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
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[(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
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// Use movzwl instead of movzwq when the destination is a register; it's
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// equivalent due to implicit zero-extending, and it has a smaller encoding.
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def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
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"movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
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[(set GR64:$dst, (zext GR16:$src))]>, TB;
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def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
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"movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
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[(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
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let neverHasSideEffects = 1 in {
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let Defs = [RAX], Uses = [EAX] in
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@ -1093,9 +1097,9 @@ def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src)
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// when we have a better way to specify isel priority.
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let Defs = [EFLAGS], AddedComplexity = 1,
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isReMaterializable = 1, isAsCheapAsAMove = 1 in
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def MOV64r0 : RI<0x31, MRMInitReg, (outs GR64:$dst), (ins),
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"xor{l}\t${dst:subreg32}, ${dst:subreg32}",
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[(set GR64:$dst, 0)]>;
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def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins),
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"xor{l}\t${dst:subreg32}, ${dst:subreg32}",
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[(set GR64:$dst, 0)]>;
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// Materialize i64 constant where top 32-bits are zero.
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let AddedComplexity = 1, isReMaterializable = 1 in
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@ -1240,6 +1244,26 @@ def : Pat<(and GR64:$src, i64immFFFFFFFF),
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(SUBREG_TO_REG (i64 0),
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(i32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)),
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x86_subreg_32bit)>;
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// r & (2^16-1) ==> movz
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def : Pat<(and GR64:$src, 0xffff),
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(MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
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// r & (2^8-1) ==> movz
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def : Pat<(and GR64:$src, 0xff),
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(MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
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// TODO: The following two patterns could be adapted to apply to x86-32, except
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// that they'll need some way to deal with the fact that in x86-32 not all GPRs
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// have 8-bit subregs. The GR32_ and GR16_ classes are a step in this direction,
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// but they aren't ready for this purpose yet.
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// r & (2^8-1) ==> movz
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def : Pat<(and GR32:$src1, 0xff),
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(MOVZX32rr8 (i8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit)))>,
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Requires<[In64BitMode]>;
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// r & (2^8-1) ==> movz
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def : Pat<(and GR16:$src1, 0xff),
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(MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
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Requires<[In64BitMode]>;
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// (shl x, 1) ==> (add x, x)
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def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
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@ -2424,12 +2424,15 @@ def CMP32ri8 : Ii8<0x83, MRM7r,
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} // Defs = [EFLAGS]
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// Sign/Zero extenders
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// Use movsbl intead of movsbw; we don't care about the high 16 bits
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// of the register here. This has a smaller encoding and avoids a
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// partial-register update.
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def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
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"movs{bw|x}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
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"movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
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[(set GR16:$dst, (sext GR8:$src))]>, TB;
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def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
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"movs{bw|x}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
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"movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
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[(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
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def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
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"movs{bl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (sext GR8:$src))]>, TB;
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@ -2443,12 +2446,15 @@ def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
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"movs{wl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
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// Use movzbl intead of movzbw; we don't care about the high 16 bits
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// of the register here. This has a smaller encoding and avoids a
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// partial-register update.
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def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
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"movz{bw|x}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
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"movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
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[(set GR16:$dst, (zext GR8:$src))]>, TB;
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def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
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"movz{bw|x}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
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"movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
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[(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
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def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
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"movz{bl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (zext GR8:$src))]>, TB;
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@ -2488,9 +2494,11 @@ let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
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"xor{b}\t$dst, $dst",
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[(set GR8:$dst, 0)]>;
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// Use xorl instead of xorw since we don't care about the high 16 bits,
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// it's smaller, and it avoids a partial-register update.
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def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
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"xor{w}\t$dst, $dst",
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[(set GR16:$dst, 0)]>, OpSize;
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"xor{l}\t${dst:subreg32}, ${dst:subreg32}",
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[(set GR16:$dst, 0)]>;
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def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
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"xor{l}\t$dst, $dst",
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[(set GR32:$dst, 0)]>;
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@ -2763,6 +2771,10 @@ def : Pat<(i32 (and (loadi32 addr:$src), (i32 65535))),(MOVZX32rm16 addr:$src)>;
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// Some peepholes
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//===----------------------------------------------------------------------===//
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// r & (2^16-1) ==> movz
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def : Pat<(and GR32:$src1, 0xffff),
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(MOVZX32rr16 (i16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit)))>;
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// (shl x, 1) ==> (add x, x)
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def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
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def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
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51
test/CodeGen/X86/zext-inreg-0.ll
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51
test/CodeGen/X86/zext-inreg-0.ll
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@ -0,0 +1,51 @@
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; RUN: llvm-as < %s | llc -march=x86 | not grep and
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; RUN: llvm-as < %s | llc -march=x86-64 > %t
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; RUN: not grep and %t
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; RUN: not grep movzbq %t
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; RUN: not grep movzwq %t
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; RUN: not grep movzlq %t
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; These should use movzbl instead of 'and 255'.
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; This related to not having a ZERO_EXTEND_REG opcode.
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define i32 @c(i32 %d) nounwind {
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%e = add i32 %d, 1
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%retval = and i32 %e, 65535
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ret i32 %retval
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}
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define i64 @e(i64 %d) nounwind {
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%e = add i64 %d, 1
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%retval = and i64 %e, 65535
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ret i64 %retval
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}
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define i64 @f(i64 %d) nounwind {
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%e = add i64 %d, 1
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%retval = and i64 %e, 4294967295
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ret i64 %retval
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}
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define i32 @g(i8 %d) nounwind {
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%e = add i8 %d, 1
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%retval = zext i8 %e to i32
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ret i32 %retval
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}
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define i32 @h(i16 %d) nounwind {
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%e = add i16 %d, 1
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%retval = zext i16 %e to i32
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ret i32 %retval
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}
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define i64 @i(i8 %d) nounwind {
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%e = add i8 %d, 1
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%retval = zext i8 %e to i64
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ret i64 %retval
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}
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define i64 @j(i16 %d) nounwind {
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%e = add i16 %d, 1
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%retval = zext i16 %e to i64
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ret i64 %retval
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}
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define i64 @k(i32 %d) nounwind {
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%e = add i32 %d, 1
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%retval = zext i32 %e to i64
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ret i64 %retval
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}
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13
test/CodeGen/X86/zext-inreg-1.ll
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13
test/CodeGen/X86/zext-inreg-1.ll
Normal file
@ -0,0 +1,13 @@
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; RUN: llvm-as < %s | llc -march=x86 | not grep and
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; These tests differ from the ones in zext-inreg-0.ll in that
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; on x86-64 they do require and instructions.
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; These should use movzbl instead of 'and 255'.
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; This related to not having ZERO_EXTEND_REG node.
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define i64 @h(i64 %d) nounwind {
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%e = add i64 %d, 1
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%retval = and i64 %e, 281474976710655
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ret i64 %retval
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}
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28
test/CodeGen/X86/zext-inreg-2.ll
Normal file
28
test/CodeGen/X86/zext-inreg-2.ll
Normal file
@ -0,0 +1,28 @@
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; RUN: llvm-as < %s | llc -march=x86-64 > %t
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; RUN: not grep and %t
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; RUN: not grep movzbq %t
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; RUN: not grep movzwq %t
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; RUN: not grep movzlq %t
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; These should use movzbl instead of 'and 255'.
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; This related to not having a ZERO_EXTEND_REG opcode.
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; This test was split out of zext-inreg-0.ll because these
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; cases don't yet work on x86-32 due to the 8-bit subreg
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; issue.
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define i32 @a(i32 %d) nounwind {
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%e = add i32 %d, 1
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%retval = and i32 %e, 255
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ret i32 %retval
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}
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define i32 @b(float %d) nounwind {
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%tmp12 = fptoui float %d to i8
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%retval = zext i8 %tmp12 to i32
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ret i32 %retval
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}
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define i64 @d(i64 %d) nounwind {
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%e = add i64 %d, 1
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%retval = and i64 %e, 255
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ret i64 %retval
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}
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