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AMDGPU/SI: Fix some invaild assumptions when folding 64-bit immediates

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Summary:
We were assuming tha if the use operand had a sub-register that
the immediate was 64-bits, but this was breaking the case of
folding a 64-bit immediate into another 64-bit instruction.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D12255

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246354 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2015-08-29 01:58:21 +00:00
parent 0554ee323c
commit 127a3d74f1
1 changed files with 5 additions and 1 deletions
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6
lib/Target/AMDGPU/SIFoldOperands.cpp
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@ -211,8 +211,12 @@ static void foldOperand(MachineOperand &OpToFold, MachineInstr *UseMI,
Imm = APInt(64, OpToFold.getImm());
const MCInstrDesc &FoldDesc = TII->get(OpToFold.getParent()->getOpcode());
const TargetRegisterClass *FoldRC =
TRI.getRegClass(FoldDesc.OpInfo[0].RegClass);
// Split 64-bit constants into 32-bits for folding.
if (UseOp.getSubReg()) {
if (FoldRC->getSize() == 8 && UseOp.getSubReg()) {
if (UseRC->getSize() != 8)
return;