[MIR] Teach the parser/printer that generic virtual registers do not need a register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262893 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/MIRParser/MIRParser.cpp

@@ -347,12 +347,19 @@ bool MIRParserImpl::initializeRegisterInfo(MachineFunction &MF,
   SMDiagnostic Error;
   // Parse the virtual register information.
   for (const auto &VReg : YamlMF.VirtualRegisters) {
-    const auto *RC = getRegClass(MF, VReg.Class.Value);
-    if (!RC)
-      return error(VReg.Class.SourceRange.Start,
-                   Twine("use of undefined register class '") +
-                       VReg.Class.Value + "'");
-    unsigned Reg = RegInfo.createVirtualRegister(RC);
+    unsigned Reg;
+    if (StringRef(VReg.Class.Value).equals("_")) {
+      // This is a generic virtual register.
+      // The size will be set appropriately when we reach the definition.
+      Reg = RegInfo.createGenericVirtualRegister(/*Size*/ 1);
+    } else {
+      const auto *RC = getRegClass(MF, VReg.Class.Value);
+      if (!RC)
+        return error(VReg.Class.SourceRange.Start,
+                     Twine("use of undefined register class '") +
+                         VReg.Class.Value + "'");
+      Reg = RegInfo.createVirtualRegister(RC);
+    }
     if (!PFS.VirtualRegisterSlots.insert(std::make_pair(VReg.ID.Value, Reg))
              .second)
       return error(VReg.ID.SourceRange.Start,

lib/CodeGen/MIRPrinter.cpp

@@ -207,8 +207,13 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
     yaml::VirtualRegisterDefinition VReg;
     VReg.ID = I;
-    VReg.Class =
-        StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
+    if (RegInfo.getRegClass(Reg))
+      VReg.Class =
+          StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
+    else {
+      VReg.Class = std::string("_");
+      assert(RegInfo.getSize(Reg) && "Generic registers must have a size");
+    }
     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
     if (PreferredReg)
       printReg(PreferredReg, VReg.PreferredRegister, TRI);

test/CodeGen/MIR/X86/generic-virtual-registers.mir

@@ -19,14 +19,17 @@
 name:            bar
 isSSA:           true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32 }
-# CHECK-NEXT:   - { id: 1, class: gr64 }
+# CHECK-NEXT:   - { id: 0, class: _ }
+# CHECK-NEXT:   - { id: 1, class: _ }
+# CHECK-NEXT:   - { id: 2, class: _ }
+# CHECK-NEXT:   - { id: 3, class: _ }
+# CHECK-NEXT:   - { id: 4, class: _ }
 registers:
-  - { id: 0, class: gr32 }
-  - { id: 1, class: gr64 }
-  - { id: 2, class: gr64 }
-  - { id: 3, class: gr64 }
-  - { id: 4, class: gr64 }
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
 body: |
   bb.0.entry:
     liveins: %edi