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Have register info provide the inverse mapping of register->superregisters. PR1350

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40519 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christopher Lamb 2007-07-26 08:01:58 +00:00
parent 08d52071ba
commit 1367fd09cb
2 changed files with 65 additions and 10 deletions
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29
include/llvm/Target/MRegisterInfo.h
View File

@ -68,6 +68,7 @@ private:
const sc_iterator SubClasses;
const sc_iterator SuperClasses;
const sc_iterator SubRegClasses;
const sc_iterator SuperRegClasses;
const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
const iterator RegsBegin, RegsEnd;
public:
@ -76,9 +77,10 @@ public:
const TargetRegisterClass * const *subcs,
const TargetRegisterClass * const *supcs,
const TargetRegisterClass * const *subregcs,
const TargetRegisterClass * const *superregcs,
unsigned RS, unsigned Al, iterator RB, iterator RE)
: ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
SubRegClasses(subregcs),
SubRegClasses(subregcs), SuperRegClasses(superregcs),
RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
virtual ~TargetRegisterClass() {} // Allow subclasses
@ -131,9 +133,9 @@ public:
return I;
}
/// hasSubRegClass - return true if the specified TargetRegisterClass is a
/// hasSubClass - return true if the specified TargetRegisterClass is a
/// sub-register class of this TargetRegisterClass.
bool hasSubRegClass(const TargetRegisterClass *cs) const {
bool hasSubClass(const TargetRegisterClass *cs) const {
for (int i = 0; SubClasses[i] != NULL; ++i)
if (SubClasses[i] == cs)
return true;
@ -152,9 +154,9 @@ public:
return I;
}
/// hasSuperRegClass - return true if the specified TargetRegisterClass is a
/// hasSuperClass - return true if the specified TargetRegisterClass is a
/// super-register class of this TargetRegisterClass.
bool hasSuperRegClass(const TargetRegisterClass *cs) const {
bool hasSuperClass(const TargetRegisterClass *cs) const {
for (int i = 0; SuperClasses[i] != NULL; ++i)
if (SuperClasses[i] == cs)
return true;
@ -173,9 +175,9 @@ public:
return I;
}
/// hasSubRegForClass - return true if the specified TargetRegisterClass is a
/// hasSubRegClass - return true if the specified TargetRegisterClass is a
/// class of a sub-register class for this TargetRegisterClass.
bool hasSubRegForClass(const TargetRegisterClass *cs) const {
bool hasSubRegClass(const TargetRegisterClass *cs) const {
for (int i = 0; SubRegClasses[i] != NULL; ++i)
if (SubRegClasses[i] == cs)
return true;
@ -199,6 +201,7 @@ public:
for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
if (i == SubReg)
return &SubRegClasses[i];
assert(0 && "Invalid subregister index for register class");
return NULL;
}
@ -214,6 +217,18 @@ public:
return I;
}
/// superregclasses_begin / superregclasses_end - Loop over all of
/// the superregister classes of this register class.
sc_iterator superregclasses_begin() const {
return SuperRegClasses;
}
sc_iterator superregclasses_end() const {
sc_iterator I = SuperRegClasses;
while (*I != NULL) ++I;
return I;
}
/// allocation_order_begin/end - These methods define a range of registers
/// which specify the registers in this class that are valid to register
/// allocate, and the preferred order to allocate them in. For example,

46
utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -223,9 +223,9 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
<< RegisterClasses[i].getName() << "RegClass;\n";
std::map<unsigned, std::set<unsigned> > SuperClassMap;
std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
OS << "\n";
// Emit the sub-register classes for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc];
@ -246,9 +246,18 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
for (; rc2 != e2; ++rc2) {
const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) {
if (!Empty) OS << ", ";
OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
if (!Empty)
OS << ", ";
OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
Empty = false;
std::map<unsigned, std::set<unsigned> >::iterator SCMI =
SuperRegClassMap.find(rc2);
if (SCMI == SuperRegClassMap.end()) {
SuperRegClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
SCMI = SuperRegClassMap.find(rc2);
}
SCMI->second.insert(rc);
break;
}
}
@ -262,6 +271,36 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
OS << "\n };\n\n";
}
// Emit the super-register classes for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc];
// Give the register class a legal C name if it's anonymous.
std::string Name = RC.TheDef->getName();
OS << " // " << Name
<< " Super-register Classess...\n"
<< " static const TargetRegisterClass* const "
<< Name << "SuperRegClasses [] = {\n ";
bool Empty = true;
std::map<unsigned, std::set<unsigned> >::iterator I =
SuperRegClassMap.find(rc);
if (I != SuperRegClassMap.end()) {
for (std::set<unsigned>::iterator II = I->second.begin(),
EE = I->second.end(); II != EE; ++II) {
const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
if (!Empty)
OS << ", ";
OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
Empty = false;
}
}
OS << (!Empty ? ", " : "") << "NULL";
OS << "\n };\n\n";
}
// Emit the sub-classes array for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc];
@ -343,6 +382,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
<< RC.getName() + "Subclasses" << ", "
<< RC.getName() + "Superclasses" << ", "
<< RC.getName() + "SubRegClasses" << ", "
<< RC.getName() + "SuperRegClasses" << ", "
<< RC.SpillSize/8 << ", "
<< RC.SpillAlignment/8 << ", " << RC.getName() << ", "
<< RC.getName() << " + " << RC.Elements.size() << ") {}\n";