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Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145680 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
826941a0af
commit
138a5c66b9
@ -14443,7 +14443,8 @@ static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
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SDValue RHS = N->getOperand(1);
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// Try to synthesize horizontal adds from adds of shuffles.
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if (Subtarget->hasSSE3orAVX() && (VT == MVT::v4f32 || VT == MVT::v2f64) &&
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if (((Subtarget->hasSSE3orAVX() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
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(Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
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isHorizontalBinOp(LHS, RHS, true))
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return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
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return SDValue();
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@ -14457,7 +14458,8 @@ static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
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SDValue RHS = N->getOperand(1);
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// Try to synthesize horizontal subs from subs of shuffles.
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if (Subtarget->hasSSE3orAVX() && (VT == MVT::v4f32 || VT == MVT::v2f64) &&
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if (((Subtarget->hasSSE3orAVX() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
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(Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
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isHorizontalBinOp(LHS, RHS, false))
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return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
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return SDValue();
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73
test/CodeGen/X86/avx2-phaddsub.ll
Normal file
73
test/CodeGen/X86/avx2-phaddsub.ll
Normal file
@ -0,0 +1,73 @@
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; RUN: llc < %s -march=x86-64 -mattr=+avx2 | FileCheck %s
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; CHECK: phaddw1:
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; CHECK: vphaddw
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define <16 x i16> @phaddw1(<16 x i16> %x, <16 x i16> %y) {
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%a = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>
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%b = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23, i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>
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%r = add <16 x i16> %a, %b
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ret <16 x i16> %r
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}
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; CHECK: phaddw2:
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; CHECK: vphaddw
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define <16 x i16> @phaddw2(<16 x i16> %x, <16 x i16> %y) {
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%a = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23, i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>
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%b = shufflevector <16 x i16> %y, <16 x i16> %x, <16 x i32> <i32 16, i32 18, i32 20, i32 22, i32 0, i32 2, i32 4, i32 6, i32 24, i32 26, i32 28, i32 30, i32 8, i32 10, i32 12, i32 14>
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%r = add <16 x i16> %a, %b
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ret <16 x i16> %r
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}
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; CHECK: phaddd1:
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; CHECK: vphaddd
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define <8 x i32> @phaddd1(<8 x i32> %x, <8 x i32> %y) {
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%a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
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%b = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
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%r = add <8 x i32> %a, %b
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ret <8 x i32> %r
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}
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; CHECK: phaddd2:
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; CHECK: vphaddd
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define <8 x i32> @phaddd2(<8 x i32> %x, <8 x i32> %y) {
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%a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 1, i32 2, i32 9, i32 10, i32 5, i32 6, i32 13, i32 14>
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%b = shufflevector <8 x i32> %y, <8 x i32> %x, <8 x i32> <i32 8, i32 11, i32 0, i32 3, i32 12, i32 15, i32 4, i32 7>
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%r = add <8 x i32> %a, %b
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ret <8 x i32> %r
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}
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; CHECK: phaddd3:
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; CHECK: vphaddd
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define <8 x i32> @phaddd3(<8 x i32> %x) {
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%a = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
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%b = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32 1, i32 3, i32 9, i32 undef, i32 5, i32 7, i32 13, i32 15>
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%r = add <8 x i32> %a, %b
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ret <8 x i32> %r
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}
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; CHECK: phsubw1:
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; CHECK: vphsubw
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define <16 x i16> @phsubw1(<16 x i16> %x, <16 x i16> %y) {
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%a = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>
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%b = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23, i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>
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%r = sub <16 x i16> %a, %b
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ret <16 x i16> %r
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}
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; CHECK: phsubd1:
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; CHECK: vphsubd
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define <8 x i32> @phsubd1(<8 x i32> %x, <8 x i32> %y) {
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%a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
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%b = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
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%r = sub <8 x i32> %a, %b
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ret <8 x i32> %r
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}
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; CHECK: phsubd2:
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; CHECK: vphsubd
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define <8 x i32> @phsubd2(<8 x i32> %x, <8 x i32> %y) {
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%a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 undef, i32 8, i32 undef, i32 4, i32 6, i32 12, i32 14>
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%b = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 1, i32 undef, i32 9, i32 11, i32 5, i32 7, i32 undef, i32 15>
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%r = sub <8 x i32> %a, %b
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ret <8 x i32> %r
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}
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@ -192,3 +192,94 @@ define <4 x float> @hsubps4(<4 x float> %x) {
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%r = fsub <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3: vhaddps1:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; SSE3: haddps
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; AVX: vhaddps1:
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; AVX: vhaddps
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define <8 x float> @vhaddps1(<8 x float> %x, <8 x float> %y) {
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%a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
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%b = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
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%r = fadd <8 x float> %a, %b
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ret <8 x float> %r
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}
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; SSE3: vhaddps2:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; SSE3: haddps
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; AVX: vhaddps2:
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; AVX: vhaddps
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define <8 x float> @vhaddps2(<8 x float> %x, <8 x float> %y) {
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%a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 1, i32 2, i32 9, i32 10, i32 5, i32 6, i32 13, i32 14>
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%b = shufflevector <8 x float> %y, <8 x float> %x, <8 x i32> <i32 8, i32 11, i32 0, i32 3, i32 12, i32 15, i32 4, i32 7>
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%r = fadd <8 x float> %a, %b
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ret <8 x float> %r
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}
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; SSE3: vhaddps3:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; SSE3: haddps
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; AVX: vhaddps3:
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; AVX: vhaddps
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define <8 x float> @vhaddps3(<8 x float> %x) {
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%a = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
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%b = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 1, i32 3, i32 9, i32 undef, i32 5, i32 7, i32 13, i32 15>
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%r = fadd <8 x float> %a, %b
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ret <8 x float> %r
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}
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; SSE3: vhsubps1:
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; SSE3-NOT: vhsubps
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; SSE3: hsubps
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; SSE3: hsubps
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; AVX: vhsubps1:
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; AVX: vhsubps
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define <8 x float> @vhsubps1(<8 x float> %x, <8 x float> %y) {
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%a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
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%b = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
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%r = fsub <8 x float> %a, %b
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ret <8 x float> %r
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}
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; SSE3: vhsubps3:
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; SSE3-NOT: vhsubps
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; SSE3: hsubps
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; SSE3: hsubps
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; AVX: vhsubps3:
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; AVX: vhsubps
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define <8 x float> @vhsubps3(<8 x float> %x) {
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%a = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
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%b = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 1, i32 3, i32 9, i32 undef, i32 5, i32 7, i32 13, i32 15>
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%r = fsub <8 x float> %a, %b
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ret <8 x float> %r
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}
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; SSE3: vhaddpd1:
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; SSE3-NOT: vhaddpd
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; SSE3: haddpd
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; SSE3: haddpd
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; AVX: vhaddpd1:
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; AVX: vhaddpd
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define <4 x double> @vhaddpd1(<4 x double> %x, <4 x double> %y) {
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%a = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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%b = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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%r = fadd <4 x double> %a, %b
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ret <4 x double> %r
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}
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; SSE3: vhsubpd1:
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; SSE3-NOT: vhsubpd
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; SSE3: hsubpd
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; SSE3: hsubpd
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; AVX: vhsubpd1:
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; AVX: vhsubpd
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define <4 x double> @vhsubpd1(<4 x double> %x, <4 x double> %y) {
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%a = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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%b = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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%r = fsub <4 x double> %a, %b
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ret <4 x double> %r
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}
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