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MachineScheduler: Limit the size of the ready list.

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Avoid quadratic complexity in unusually large basic blocks by limiting
the size of the ready lists.

Differential Revision: http://reviews.llvm.org/D19349

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267189 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun 2016-04-22 19:09:17 +00:00
parent c6ee1a00f8
commit 14c1739a3e
2 changed files with 11 additions and 1 deletions
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11
lib/CodeGen/MachineScheduler.cpp
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@ -64,6 +64,11 @@ static cl::opt<unsigned> SchedOnlyBlock("misched-only-block", cl::Hidden,
static bool ViewMISchedDAGs = false;
#endif // NDEBUG
/// Avoid quadratic complexity in unusually large basic blocks by limiting the
/// size of the ready lists.
static cl::opt<unsigned> ReadyListLimit("misched-limit", cl::Hidden,
cl::desc("Limit ready list to N instructions"), cl::init(256));
static cl::opt<bool> EnableRegPressure("misched-regpressure", cl::Hidden,
cl::desc("Enable register pressure scheduling."), cl::init(true));
@ -1956,7 +1961,8 @@ void SchedBoundary::releaseNode(SUnit *SU, unsigned ReadyCycle) {
// Check for interlocks first. For the purpose of other heuristics, an
// instruction that cannot issue appears as if it's not in the ReadyQueue.
bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
if ((!IsBuffered && ReadyCycle > CurrCycle) || checkHazard(SU))
if ((!IsBuffered && ReadyCycle > CurrCycle) || checkHazard(SU) ||
Available.size() >= ReadyListLimit)
Pending.push(SU);
else
Available.push(SU);
@ -2211,6 +2217,9 @@ void SchedBoundary::releasePending() {
if (checkHazard(SU))
continue;
if (Available.size() >= ReadyListLimit)
break;
Available.push(SU);
Pending.remove(Pending.begin()+i);
--i; --e;

1
test/CodeGen/AArch64/arm64-misched-basic-A53.ll
View File

@ -1,5 +1,6 @@
; REQUIRES: asserts
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - -misched-limit=2 2>&1 > /dev/null | FileCheck %s
;
; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
; much higher than the ADD instructions in order to hide latency. When not