From 152ac18e80fd964852352efe0f7bcdff49364d95 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Thu, 4 Dec 2014 03:41:21 +0000 Subject: [PATCH] [Hexagon] Marking some instructions as CodeGenOnly=0 and adding disassembly tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223334 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../Disassembler/HexagonDisassembler.cpp | 5 ++++- lib/Target/Hexagon/Disassembler/LLVMBuild.txt | 2 +- lib/Target/Hexagon/HexagonInstrInfo.td | 5 ++++- test/MC/Disassembler/Hexagon/alu32_alu.txt | 18 ++++++++++++++++++ 4 files changed, 27 insertions(+), 3 deletions(-) create mode 100644 test/MC/Disassembler/Hexagon/alu32_alu.txt diff --git a/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index bc64be17b97..72ba2f5ea54 100644 --- a/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -8,6 +8,7 @@ //===----------------------------------------------------------------------===// #include "MCTargetDesc/HexagonBaseInfo.h" +#include "MCTargetDesc/HexagonMCInst.h" #include "MCTargetDesc/HexagonMCTargetDesc.h" #include "llvm/MC/MCContext.h" @@ -110,5 +111,7 @@ DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, // Remove parse bits. insn &= ~static_cast(HexagonII::InstParseBits::INST_PARSE_MASK); - return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI); + DecodeStatus Result = decodeInstruction(DecoderTable32, MI, insn, Address, this, STI); + HexagonMCInst::AppendImplicitOperands(MI); + return Result; } diff --git a/lib/Target/Hexagon/Disassembler/LLVMBuild.txt b/lib/Target/Hexagon/Disassembler/LLVMBuild.txt index 17ad11bd535..43bace75a85 100644 --- a/lib/Target/Hexagon/Disassembler/LLVMBuild.txt +++ b/lib/Target/Hexagon/Disassembler/LLVMBuild.txt @@ -19,5 +19,5 @@ type = Library name = HexagonDisassembler parent = Hexagon -required_libraries = HexagonInfo MCDisassembler Support +required_libraries = HexagonDesc HexagonInfo MCDisassembler Support add_to_library_groups = Hexagon diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index 9bcb07e90c0..94448f74a08 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -170,12 +170,13 @@ multiclass T_ALU32_3op_A2 MajOp, bits<3> MinOp, defm A2_p#NAME : T_ALU32_3op_p; } -let isCodeGenOnly = 0 in +let isCodeGenOnly = 0 in { defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>; defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>; defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>; defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>; defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>; +} // Pats for instruction selection. class BinOp32_pat @@ -275,11 +276,13 @@ multiclass ALU32_2op_base minOp> { } } +let isCodeGenOnly = 0 in { defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel; defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel; defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel; defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel; defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel; +} // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255). // Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has diff --git a/test/MC/Disassembler/Hexagon/alu32_alu.txt b/test/MC/Disassembler/Hexagon/alu32_alu.txt new file mode 100644 index 00000000000..3c2d4cd6932 --- /dev/null +++ b/test/MC/Disassembler/Hexagon/alu32_alu.txt @@ -0,0 +1,18 @@ +# XFAIL: arm-windows +# XFAIL: arm-linux +# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s + +0x11 0xdf 0x15 0xf3 +# CHECK: r17 = add(r21, r31) +0x11 0xdf 0x15 0xf1 +# CHECK: r17 = and(r21, r31) +0x11 0xdf 0x35 0xf1 +# CHECK: r17 = or(r21, r31) +0x11 0xdf 0x75 0xf1 +# CHECK: r17 = xor(r21, r31) +0x11 0xdf 0x35 0xf3 +# CHECK: r17 = sub(r31, r21) +0x11 0xc0 0xbf 0x70 +# CHECK: r17 = sxtb(r31) +0x11 0xc0 0xd5 0x70 +# CHECK: r17 = zxth(r21)