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Few targets like PIC16 wants libcall generation for illegal type i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62467 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -29,15 +29,19 @@ namespace RTLIB {
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///
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enum Libcall {
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// Integer
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SHL_I16,
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SHL_I32,
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SHL_I64,
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SHL_I128,
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SRL_I16,
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SRL_I32,
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SRL_I64,
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SRL_I128,
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SRA_I16,
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SRA_I32,
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SRA_I64,
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SRA_I128,
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MUL_I16,
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MUL_I32,
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MUL_I64,
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MUL_I128,
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@ -1586,7 +1586,9 @@ void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
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// If nothing else, we can make a libcall.
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RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
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if (VT == MVT::i32)
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if (VT == MVT::i16)
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LC = RTLIB::MUL_I16;
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else if (VT == MVT::i32)
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LC = RTLIB::MUL_I32;
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else if (VT == MVT::i64)
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LC = RTLIB::MUL_I64;
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@ -1662,7 +1664,9 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
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bool isSigned;
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if (N->getOpcode() == ISD::SHL) {
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isSigned = false; /*sign irrelevant*/
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if (VT == MVT::i32)
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if (VT == MVT::i16)
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LC = RTLIB::SHL_I16;
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else if (VT == MVT::i32)
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LC = RTLIB::SHL_I32;
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else if (VT == MVT::i64)
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LC = RTLIB::SHL_I64;
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@ -1670,7 +1674,9 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
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LC = RTLIB::SHL_I128;
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} else if (N->getOpcode() == ISD::SRL) {
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isSigned = false;
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if (VT == MVT::i32)
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if (VT == MVT::i16)
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LC = RTLIB::SRL_I16;
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else if (VT == MVT::i32)
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LC = RTLIB::SRL_I32;
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else if (VT == MVT::i64)
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LC = RTLIB::SRL_I64;
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@ -1679,7 +1685,9 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
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} else {
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assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
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isSigned = true;
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if (VT == MVT::i32)
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if (VT == MVT::i16)
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LC = RTLIB::SRA_I16;
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else if (VT == MVT::i32)
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LC = RTLIB::SRA_I32;
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else if (VT == MVT::i64)
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LC = RTLIB::SRA_I64;
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@ -29,15 +29,19 @@ using namespace llvm;
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/// InitLibcallNames - Set default libcall names.
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///
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static void InitLibcallNames(const char **Names) {
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Names[RTLIB::SHL_I16] = "__ashli16";
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Names[RTLIB::SHL_I32] = "__ashlsi3";
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Names[RTLIB::SHL_I64] = "__ashldi3";
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Names[RTLIB::SHL_I128] = "__ashlti3";
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Names[RTLIB::SRL_I16] = "__lshri16";
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Names[RTLIB::SRL_I32] = "__lshrsi3";
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Names[RTLIB::SRL_I64] = "__lshrdi3";
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Names[RTLIB::SRL_I128] = "__lshrti3";
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Names[RTLIB::SRA_I16] = "__ashri16";
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Names[RTLIB::SRA_I32] = "__ashrsi3";
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Names[RTLIB::SRA_I64] = "__ashrdi3";
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Names[RTLIB::SRA_I128] = "__ashrti3";
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Names[RTLIB::MUL_I16] = "__muli16";
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Names[RTLIB::MUL_I32] = "__mulsi3";
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Names[RTLIB::MUL_I64] = "__muldi3";
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Names[RTLIB::MUL_I128] = "__multi3";
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