RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2025-02-07 04:46:52 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[Hexagon] Fix/simplify some conditional statements

Browse Source 
Fix for PR28138.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272836 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek 2016-06-15 21:05:04 +00:00
parent f258b9a271
commit 16185a2b7f
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -1530,7 +1530,7 @@ bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
unsigned SizeA = 0, SizeB = 0;
if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() ||
MIa->hasOrderedMemoryRef() || MIa->hasOrderedMemoryRef())
MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
return false;
// Instructions that are pure loads, not loads and stores like memops are not
@ -3673,8 +3673,8 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
case Hexagon::S4_storeirb_io:
// memb(Rs+#u4) = #U1
Src1Reg = MI->getOperand(0).getReg();
if (isIntRegForSubInst(Src1Reg) && MI->getOperand(1).isImm() &&
isUInt<4>(MI->getOperand(1).getImm()) && MI->getOperand(2).isImm() &&
if (isIntRegForSubInst(Src1Reg) &&
MI->getOperand(1).isImm() && isUInt<4>(MI->getOperand(1).getImm()) &&
MI->getOperand(2).isImm() && isUInt<1>(MI->getOperand(2).getImm()))
return HexagonII::HSIG_S2;
break;