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MC: Remove MCSubtargetInfo() default constructor

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Force all creators of `MCSubtargetInfo` to immediately initialize it,
merging the default constructor and the initializer into an initializing
constructor.  Besides cleaning up the code a little, this makes it clear
that the initializer is never called again later.

Out-of-tree backends need a trivial change: instead of calling:

    auto *X = new MCSubtargetInfo();
    InitXYZMCSubtargetInfo(X, ...);
    return X;

they should call:

    return createXYZMCSubtargetInfoImpl(...);

There's no real functionality change here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241957 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan P. N. Exon Smith 2015-07-10 22:43:42 +00:00
parent 5733fd14d4
commit 16859aa242
18 changed files with 51 additions and 73 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
include/llvm/MC/MCSubtargetInfo.h
View File

@ -44,15 +44,16 @@ class MCSubtargetInfo {
const unsigned *ForwardingPaths; // Forwarding paths
FeatureBitset FeatureBits; // Feature bits for current CPU + FS
MCSubtargetInfo() = delete;
public:
void InitMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF,
ArrayRef<SubtargetFeatureKV> PD,
const SubtargetInfoKV *ProcSched,
const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA, const InstrStage *IS,
const unsigned *OC, const unsigned *FP);
MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF,
ArrayRef<SubtargetFeatureKV> PD,
const SubtargetInfoKV *ProcSched,
const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA, const InstrStage *IS,
const unsigned *OC, const unsigned *FP);
/// getTargetTriple - Return the target triple string.
const Triple &getTargetTriple() const { return TargetTriple; }

10
include/llvm/Target/TargetSubtargetInfo.h
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@ -44,9 +44,17 @@ template <typename T> class SmallVectorImpl;
class TargetSubtargetInfo : public MCSubtargetInfo {
TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
void operator=(const TargetSubtargetInfo &) = delete;
TargetSubtargetInfo() = delete;
protected: // Can only create subclasses...
TargetSubtargetInfo();
TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF,
ArrayRef<SubtargetFeatureKV> PD,
const SubtargetInfoKV *ProcSched,
const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA, const InstrStage *IS,
const unsigned *OC, const unsigned *FP);
public:
// AntiDepBreakMode - Type of anti-dependence breaking that should

20
lib/MC/MCSubtargetInfo.cpp
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@ -29,25 +29,15 @@ MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
}
void MCSubtargetInfo::InitMCSubtargetInfo(
MCSubtargetInfo::MCSubtargetInfo(
const Triple &TT, StringRef C, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
const InstrStage *IS, const unsigned *OC, const unsigned *FP) {
TargetTriple = TT;
CPU = C;
ProcFeatures = PF;
ProcDesc = PD;
ProcSchedModels = ProcSched;
WriteProcResTable = WPR;
WriteLatencyTable = WL;
ReadAdvanceTable = RA;
Stages = IS;
OperandCycles = OC;
ForwardingPaths = FP;
const InstrStage *IS, const unsigned *OC, const unsigned *FP)
: TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL),
ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
InitMCProcessorInfo(CPU, FS);
}

5
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
View File

@ -42,13 +42,10 @@ static MCInstrInfo *createAArch64MCInstrInfo() {
static MCSubtargetInfo *
createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
if (CPU.empty())
CPU = "generic";
InitAArch64MCSubtargetInfo(X, TT, CPU, FS);
return X;
return createAArch64MCSubtargetInfoImpl(TT, CPU, FS);
}
static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {

4
lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
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@ -52,9 +52,7 @@ static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *
createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo * X = new MCSubtargetInfo();
InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
return X;
return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
}
static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(const Triple &TT,

4
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
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@ -257,9 +257,7 @@ MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
ArchFS = FS;
}
MCSubtargetInfo *X = new MCSubtargetInfo();
InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
return X;
return createARMMCSubtargetInfoImpl(TT, CPU, ArchFS);
}
static MCInstrInfo *createARMMCInstrInfo() {

4
lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
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@ -48,9 +48,7 @@ static MCRegisterInfo *createBPFMCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *createBPFMCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitBPFMCSubtargetInfo(X, TT, CPU, FS);
return X;
return createBPFMCSubtargetInfoImpl(TT, CPU, FS);
}
static MCCodeGenInfo *createBPFMCCodeGenInfo(const Triple &TT, Reloc::Model RM,

4
lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
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@ -54,9 +54,7 @@ static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *
createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitHexagonMCSubtargetInfo(X, TT, CPU, FS);
return X;
return createHexagonMCSubtargetInfoImpl(TT, CPU, FS);
}
namespace {

4
lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
View File

@ -45,9 +45,7 @@ static MCRegisterInfo *createMSP430MCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *
createMSP430MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitMSP430MCSubtargetInfo(X, TT, CPU, FS);
return X;
return createMSP430MCSubtargetInfoImpl(TT, CPU, FS);
}
static MCCodeGenInfo *createMSP430MCCodeGenInfo(const Triple &TT,

4
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
View File

@ -68,9 +68,7 @@ static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef FS) {
CPU = MIPS_MC::selectMipsCPU(TT, CPU);
MCSubtargetInfo *X = new MCSubtargetInfo();
InitMipsMCSubtargetInfo(X, TT, CPU, FS);
return X;
return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
}
static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,

4
lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
View File

@ -46,9 +46,7 @@ static MCRegisterInfo *createNVPTXMCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *
createNVPTXMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitNVPTXMCSubtargetInfo(X, TT, CPU, FS);
return X;
return createNVPTXMCSubtargetInfoImpl(TT, CPU, FS);
}
static MCCodeGenInfo *createNVPTXMCCodeGenInfo(const Triple &TT,

4
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
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@ -64,9 +64,7 @@ static MCRegisterInfo *createPPCMCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *createPPCMCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitPPCMCSubtargetInfo(X, TT, CPU, FS);
return X;
return createPPCMCSubtargetInfoImpl(TT, CPU, FS);
}
static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI,

4
lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
View File

@ -65,11 +65,9 @@ static MCRegisterInfo *createSparcMCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *
createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
if (CPU.empty())
CPU = (TT.getArch() == Triple::sparcv9) ? "v9" : "v8";
InitSparcMCSubtargetInfo(X, TT, CPU, FS);
return X;
return createSparcMCSubtargetInfoImpl(TT, CPU, FS);
}
// Code models. Some only make sense for 64-bit code.

4
lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
View File

@ -156,9 +156,7 @@ static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *
createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitSystemZMCSubtargetInfo(X, TT, CPU, FS);
return X;
return createSystemZMCSubtargetInfoImpl(TT, CPU, FS);
}
static MCCodeGenInfo *createSystemZMCCodeGenInfo(const Triple &TT,

9
lib/Target/TargetSubtargetInfo.cpp
View File

@ -19,7 +19,14 @@ using namespace llvm;
//---------------------------------------------------------------------------
// TargetSubtargetInfo Class
//
TargetSubtargetInfo::TargetSubtargetInfo() {}
TargetSubtargetInfo::TargetSubtargetInfo(
const Triple &TT, StringRef CPU, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
const InstrStage *IS, const unsigned *OC, const unsigned *FP)
: MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
}
TargetSubtargetInfo::~TargetSubtargetInfo() {}

4
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
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@ -88,9 +88,7 @@ MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
if (CPUName.empty())
CPUName = "generic";
MCSubtargetInfo *X = new MCSubtargetInfo();
InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
return X;
return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS);
}
static MCInstrInfo *createX86MCInstrInfo() {

4
lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
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@ -48,9 +48,7 @@ static MCRegisterInfo *createXCoreMCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *
createXCoreMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitXCoreMCSubtargetInfo(X, TT, CPU, FS);
return X;
return createXCoreMCSubtargetInfoImpl(TT, CPU, FS);
}
static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI,

15
utils/TableGen/SubtargetEmitter.cpp
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@ -1435,10 +1435,10 @@ void SubtargetEmitter::run(raw_ostream &OS) {
#endif
// MCInstrInfo initialization routine.
OS << "static inline void Init" << Target
<< "MCSubtargetInfo(MCSubtargetInfo *II, "
OS << "static inline MCSubtargetInfo *create" << Target
<< "MCSubtargetInfoImpl("
<< "const Triple &TT, StringRef CPU, StringRef FS) {\n";
OS << " II->InitMCSubtargetInfo(TT, CPU, FS, ";
OS << " return new MCSubtargetInfo(TT, CPU, FS, ";
if (NumFeatures)
OS << Target << "FeatureKV, ";
else
@ -1518,8 +1518,7 @@ void SubtargetEmitter::run(raw_ostream &OS) {
OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, "
<< "StringRef FS)\n"
<< " : TargetSubtargetInfo() {\n"
<< " InitMCSubtargetInfo(TT, CPU, FS, ";
<< " : TargetSubtargetInfo(TT, CPU, FS, ";
if (NumFeatures)
OS << "makeArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), ";
else
@ -1528,19 +1527,19 @@ void SubtargetEmitter::run(raw_ostream &OS) {
OS << "makeArrayRef(" << Target << "SubTypeKV, " << NumProcs << "), ";
else
OS << "None, ";
OS << '\n'; OS.indent(22);
OS << '\n'; OS.indent(24);
OS << Target << "ProcSchedKV, "
<< Target << "WriteProcResTable, "
<< Target << "WriteLatencyTable, "
<< Target << "ReadAdvanceTable, ";
OS << '\n'; OS.indent(22);
OS << '\n'; OS.indent(24);
if (SchedModels.hasItineraries()) {
OS << Target << "Stages, "
<< Target << "OperandCycles, "
<< Target << "ForwardingPaths";
} else
OS << "0, 0, 0";
OS << ");\n}\n\n";
OS << ") {}\n\n";
EmitSchedModelHelpers(ClassName, OS);